This document covers the configuration and usage of the Hardware Abstraction Layer (HAL) for the Hard Processor System (HPS) present on the Cyclone V FPGA. It is expected to be read in conjunction with platform HAL-specific documentation, as well as the eCos HAL specification. This processor HAL package complements the ARM architectural HAL, Cortex-A variant HAL and the platform HAL. It provides functionality common to all HPS-based implementations.
This support is found in the eCos package located at packages/hal/arm/cortexa/altera_hps within the eCos source repository.
The Altera HPS HAL package is loaded automatically when eCos is configured for an HPS-based platform. It should never be necessary to load this package explicitly. Unloading the package should only happen as a side effect of switching target hardware.
Supported features of the HPS within this processor HAL package include:
Support for the on-chip QSPI device, SPI NOR flash, interrupt-driven serial, watchdog and wallclock (RTC) features of the HPS are also present and can be found in separate packages, outside of this processor HAL.
Support for SMP operation of the two Cortex-A9 CPUs in the HPS is available, although debugging support is restricted to use of an external JTAG debugger. The HAL does not contain support for the Cortex-A's NEON SIMD engine.