Interrupt controller definitions
The file <cyg/hal/var_ints.h> (located at hal/arm/cortexa/altera_hps/VERSION/include/var_ints.h in the eCos source repository) contains interrupt vector number definitions for use with the eCos kernel and driver interrupt APIs.
The list of interrupt vectors may be augmented on a per-platform basis. Consult the platform HAL documentation for your platform for whether this is the case.
Interrupt Controller Functions
The HPS uses a standard ARM Generic Interrupt Controller (GIC),
which is implemented in the Cortex-A HAL. The Cortex-A HAL exports
the standard interrupt vector management functions. The
hal_IRQ_handler queries the IRQ status
register to determine the interrupt cause. Functions
hal_interrupt_unmask enable or disable
interrupts within the interrupt controller.
Interrupts are configured in the
hal_interrupt_configure function. Refer to
the HPS documentation for any limitations as to what types of
signal can be detected.
hal_interrupt_eoi function performs
End-Of-Interrupt processing and is called automatically by the
architecture HAL. The
hal_interrupt_acknowledge function is
intended to acknowledge an interrupt, although for the GIC it is a
NUL function since the necessary work it handled by the EOI
hal_interrupt_set_level is used to set
the priority level of the supplied interrupt within the
GIC. Priorities may range between 0 and 255, with lower values
mapping to higher priority. The GIC in the HPS only implements the
top 5 bits of the priority value, so there are actually 32
distinct priority levels available.
Note that in all the above, it is not recommended to call the
described functions directly. Instead either the HAL macros
HAL_INTERRUPT_MASK et al) or preferably the
kernel or driver APIs should be used to control interrupts.