The I2C driver in the
CYGPKG_DEVS_I2C_DWI2C supports the use of I2C
devices within eCos. Access to the driver will be via the standard
I2C interface subsystem.
This driver provides support for all four I2C busses available on the HPS. The number of interfaces supported is defined by the platform HAL.
The HAL contains the following configuration options for each the I2C busses:
This interface controls the inclusion of support for I2C bus X. This will normally be implemented by the platform HAL to indicate that there are I2C devices attached to the given bus, or that the SCL and SDA lines are routed to an external connector.
This is the I2C bus X clock speed in Hz. Frequencies of either 100kHz or 400kHz can be chosen, the latter sometimes known as fast mode.
This is the I2C bus X interrupt priority. It may range from 1 to 255; the default of 128 places it in the centre of the priority range.
The design of the I2C device does not make it possible to start a new bus transfer without also sending a START condition on the bus. This means that divided transactions are not possible. A divided transaction would look like this:
cyg_i2c_transaction_begin(&cyg_aardvark_at24c02); cyg_i2c_transaction_tx(&cyg_aardvark_at24c02, 1, tx_buf1, 1, 0); cyg_i2c_transaction_tx(&cyg_aardvark_at24c02, 0, tx_buf2, 2, 0); cyg_i2c_transaction_tx(&cyg_aardvark_at24c02, 0, tx_buf3, 6, 1); cyg_i2c_transaction_end(&cyg_aardvark_at24c02);
In this transaction a START and one byte are sent from tx_buf1, then 2 bytes of data from tx_buf2, finishing with 6 bytes from tx_buf3 followed by a STOP. The device will not allow the tx_buf2 and tx_buf3 transfers to happen without also sending a START. The only solution to this is to combine the data into a single buffer and perform a single transfer:
memcpy( tx_buf, tx_buf1, 1); memcpy( tx_buf+1, tx_buf2, 2); memcpy( tx_buf+3, tx_buf3, 6); cyg_i2c_tx(&cyg_aardvark_at24c02, tx_buf, 9);