| The HAL Port | ||
|---|---|---|
 | Chapter 304. STM32F4DISCOVERY Platform HAL |  |
Name
HAL Port — Implementation Details
Overview
This documentation explains how the eCos HAL specification has been mapped onto the STM32F4DISCOVERY board hardware and should be read in conjunction with that specification. The STM32F4DISCOVERY platform HAL package complements the Cortex-M architectural HAL and the STM32 variant HAL. It provides functionality which is specific to the target board.
Startup
Following a hard or soft reset the HAL will initialize or reinitialize many of the on-chip peripherals. There is an exception for RAM startup applications which depend on a ROM monitor for certain services.
For ROM and JTAG startup, the
HAL will perform additional initialization, programming the various
internal registers including the PLL, peripheral clocks and GPIO
pins. The details of the early hardware startup may be found in
the src/stm32f4dis_misc.c in
both hal_system_init
and hal_platform_init.
Memory Map
The platform HAL package provides the memory layout information needed to generate the linker script. The key memory locations are as follows:
- Internal RAM
This is located at address
0x20000000of the memory space, and is 128KiB in size. The eCos VSR table occupies the bottom 392-bytes. The virtual vector table starts at0x20000188and extends to0x20000288. ForROM, andJTAGstartups, the topCYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZEbytes are reserved for the interrupt stack. The remainder of internal RAM is available for use by applications.- Internal FLASH
This is located at address
0x08000000of the memory space and will be mapped to0x00000000at reset. This region is 1MiB in size. ROM applications are by default configured to run from this memory.- On-Chip Peripherals
These are accessible at locations
0x40000000and0xE0000000upwards. Descriptions of the contents can be found in the STM32F4 Reference Manual (RM0090).
Linker Scripts
The platform linker scripts define the following symbols:
- hal_vsr_table
This defines the location of the VSR table. This is set to
0x20000000for all startup types, and space for 98 entries is reserved due to the use of the STM32F4 processor.- hal_virtual_vector_table
This defines the location of the virtual vector table used to communicate between an ROM monitor and an eCos application. This is allocated right after the VSR table, at
0x20000188.- hal_interrupt_stack
This defines the location of the interrupt stack. For all startup types this is allocated to the top of available internal SRAM, which is normally
0x20020000.- hal_startup_stack
This defines the location of the startup stack. For all startup types it is initially allocated at the half-way point of the interrupt stack.
Diagnostic LEDs
Four LEDs are fitted on the board for diagnostic purposes:
| Platform HAL manifest | Colour | Board Label |
|---|---|---|
CYGHWR_HAL_STM32F4DIS_LED0
| Orange |
LD3
|
CYGHWR_HAL_STM32F4DIS_LED1
| Green |
LD4
|
CYGHWR_HAL_STM32F4DIS_LED2
| Red |
LD5
|
CYGHWR_HAL_STM32F4DIS_LED3
| Blue |
LD6
|
The platform HAL header file
at <cyg/hal/plf_io.h>
defines the following convenience function to allow the LEDs to be
set:
extern void hal_stm32f4dis_led(char c);
The lowest 4-bits of the argument c correspond to
each of the 4 LEDs (with LED0 as the least significant bit).
The platform HAL will automatically light LED0 when the platform initialisation is complete, however the LEDs are free for application use.
Flash wait states
The STM32F4DISCOVERY platform HAL provides a configuration option to
set the number of Flash read wait states to use:
CYGNUM_HAL_CORTEXM_STM32_FLASH_WAIT_STATES. It is
important to verify and if necessary update this value if changing the
CPU clock (HCLK) frequency or CPU voltage. Consult the STM32F40xxx Flash
programming manual (PM0081) for appropriate values for different clock
speeds or voltages. The default of 5 reflects a supply voltage of 3.3V
and HCLK of 168MHz.
Real-time characterization
The tm_basic kernel test gives statistics gathered
about the real-time characterization and performance of the
kernel. The sample output is shown here for information. The test was
built for JTAG startup with optimization flag -O2.
Example 304.1. stm32f4dis Real-time characterization
Startup, main stack : stack used 84 size 1536
Startup : Idlethread stack used 80 size 1280
eCos Kernel Timings
Notes: all times are in microseconds (.000001) unless otherwise stated
Reading the hardware clock takes 0 'ticks' overhead
... this value will be factored out of all other measurements
Clock interrupt took 4.13 microseconds (4 raw clock ticks)
Testing parameters:
Clock samples: 32
Threads: 6
Thread switches: 128
Mutexes: 32
Mailboxes: 32
Semaphores: 32
Scheduler operations: 128
Counters: 32
Flags: 32
Alarms: 32
Stack Size: 1096
Confidence
Ave Min Max Var Ave Min Function
====== ====== ====== ====== ========== ========
4.67 4.00 5.00 0.44 66% 33% Create thread
1.00 1.00 1.00 0.00 100% 100% Yield thread [all suspended]
1.00 1.00 1.00 0.00 100% 100% Suspend [suspended] thread
1.00 1.00 1.00 0.00 100% 100% Resume thread
1.67 1.00 2.00 0.44 66% 33% Set priority
0.00 0.00 0.00 0.00 100% 100% Get priority
2.83 2.00 3.00 0.28 83% 16% Kill [suspended] thread
1.00 1.00 1.00 0.00 100% 100% Yield [no other] thread
1.50 1.00 2.00 0.50 100% 50% Resume [suspended low prio] thread
1.00 1.00 1.00 0.00 100% 100% Resume [runnable low prio] thread
1.17 1.00 2.00 0.28 83% 83% Suspend [runnable] thread
1.00 1.00 1.00 0.00 100% 100% Yield [only low prio] thread
1.00 1.00 1.00 0.00 100% 100% Suspend [runnable->not runnable]
2.67 2.00 3.00 0.44 66% 33% Kill [runnable] thread
2.50 2.00 3.00 0.50 100% 50% Destroy [dead] thread
4.33 4.00 5.00 0.44 66% 66% Destroy [runnable] thread
5.17 5.00 6.00 0.28 83% 83% Resume [high priority] thread
1.86 1.00 2.00 0.24 85% 14% Thread switch
0.21 0.00 1.00 0.33 78% 78% Scheduler lock
0.80 0.00 1.00 0.31 80% 19% Scheduler unlock [0 threads]
0.85 0.00 1.00 0.25 85% 14% Scheduler unlock [1 suspended]
0.84 0.00 1.00 0.27 83% 16% Scheduler unlock [many suspended]
0.88 0.00 1.00 0.22 87% 12% Scheduler unlock [many low prio]
0.22 0.00 1.00 0.34 78% 78% Init mutex
1.19 1.00 2.00 0.30 81% 81% Lock [unlocked] mutex
1.44 1.00 2.00 0.49 56% 56% Unlock [locked] mutex
1.13 1.00 2.00 0.22 87% 87% Trylock [unlocked] mutex
0.97 0.00 1.00 0.06 96% 3% Trylock [locked] mutex
0.28 0.00 1.00 0.40 71% 71% Destroy mutex
6.00 6.00 6.00 0.00 100% 100% Unlock/Lock mutex
0.44 0.00 1.00 0.49 56% 56% Create mbox
0.19 0.00 1.00 0.30 81% 81% Peek [empty] mbox
1.19 1.00 2.00 0.30 81% 81% Put [first] mbox
0.16 0.00 1.00 0.26 84% 84% Peek [1 msg] mbox
1.19 1.00 2.00 0.30 81% 81% Put [second] mbox
0.22 0.00 1.00 0.34 78% 78% Peek [2 msgs] mbox
1.28 1.00 2.00 0.40 71% 71% Get [first] mbox
1.19 1.00 2.00 0.30 81% 81% Get [second] mbox
1.03 1.00 2.00 0.06 96% 96% Tryput [first] mbox
1.03 1.00 2.00 0.06 96% 96% Peek item [non-empty] mbox
1.16 1.00 2.00 0.26 84% 84% Tryget [non-empty] mbox
1.00 1.00 1.00 0.00 100% 100% Peek item [empty] mbox
1.00 1.00 1.00 0.00 100% 100% Tryget [empty] mbox
0.22 0.00 1.00 0.34 78% 78% Waiting to get mbox
0.22 0.00 1.00 0.34 78% 78% Waiting to put mbox
0.44 0.00 1.00 0.49 56% 56% Delete mbox
3.84 3.00 4.00 0.26 84% 15% Put/Get mbox
0.28 0.00 1.00 0.40 71% 71% Init semaphore
0.97 0.00 1.00 0.06 96% 3% Post [0] semaphore
1.00 1.00 1.00 0.00 100% 100% Wait [1] semaphore
0.97 0.00 1.00 0.06 96% 3% Trywait [0] semaphore
1.00 1.00 1.00 0.00 100% 100% Trywait [1] semaphore
0.25 0.00 1.00 0.38 75% 75% Peek semaphore
0.41 0.00 1.00 0.48 59% 59% Destroy semaphore
3.78 3.00 4.00 0.34 78% 21% Post/Wait semaphore
0.47 0.00 1.00 0.50 53% 53% Create counter
0.34 0.00 1.00 0.45 65% 65% Get counter value
0.16 0.00 1.00 0.26 84% 84% Set counter value
1.09 1.00 2.00 0.17 90% 90% Tick counter
0.34 0.00 1.00 0.45 65% 65% Delete counter
0.31 0.00 1.00 0.43 68% 68% Init flag
1.09 1.00 2.00 0.17 90% 90% Destroy flag
0.97 0.00 1.00 0.06 96% 3% Mask bits in flag
1.00 1.00 1.00 0.00 100% 100% Set bits in flag [no waiters]
1.56 1.00 2.00 0.49 56% 43% Wait for flag [AND]
1.50 1.00 2.00 0.50 100% 50% Wait for flag [OR]
1.56 1.00 2.00 0.49 56% 43% Wait for flag [AND/CLR]
1.50 1.00 2.00 0.50 100% 50% Wait for flag [OR/CLR]
0.25 0.00 1.00 0.38 75% 75% Peek on flag
0.63 0.00 1.00 0.47 62% 37% Create alarm
1.63 1.00 2.00 0.47 62% 37% Initialize alarm
0.97 0.00 1.00 0.06 96% 3% Disable alarm
1.50 1.00 2.00 0.50 100% 50% Enable alarm
1.06 1.00 2.00 0.12 93% 93% Delete alarm
1.25 1.00 2.00 0.38 75% 75% Tick counter [1 alarm]
8.66 8.00 9.00 0.45 65% 34% Tick counter [many alarms]
2.22 2.00 3.00 0.34 78% 78% Tick & fire counter [1 alarm]
39.91 39.00 40.00 0.17 90% 9% Tick & fire counters [>1 together]
9.59 9.00 10.00 0.48 59% 40% Tick & fire counters [>1 separately]
4.00 4.00 4.00 0.00 100% 100% Alarm latency [0 threads]
3.25 3.00 4.00 0.38 75% 75% Alarm latency [2 threads]
3.22 3.00 4.00 0.34 78% 78% Alarm latency [many threads]
7.01 7.00 8.00 0.01 99% 99% Alarm -> thread resume latency
224 220 228 (main stack: 877) Thread stack used (1096 total)
All done, main stack : stack used 877 size 1536
All done : Idlethread stack used 168 size 1280
Timing complete - 27850 ms total
PASS:<Basic timing OK>
EXIT:<done>| |  | |
| JTAG/SWD debugging support |  | Chapter 305. STM324X9I-EVAL Platform HAL |
| 2024-03-18 | eCosPro Non-Commercial Public License |