SAMA5D3x-CM Platform HAL

Name

CYGPKG_HAL_ARM_CORTEXA_SAMA5D3X_CM -- eCos Support for the SAMA5D3x-CM CPU Module

Description

There are currently two supported variants of CPU Module (CM). The Embest/Flextronics “SAMA5D3x-CM_rev.E” and the Ronetix “SAMA5D3x-CM v2.0” daughterboards. The boards can be identified by the silk screened names on the respective PCBs.

The currently supported CM variants are identical in functionality, with the exception of the type of NOR flash installed on EBI_CS0. However, the eCos port is configured to allow a single binary to execute irrespective of the installed CPU Module.

The common CM features include 512MiB of DDR2-SDRAM, 16MiB NOR flash, routing for the 10/100 EMAC, and blue and red LEDs. Some common CM features are not yet supported by the eCos port, e.g. NAND.

For typical eCos development it is expected that hardware debugging will be used, as detailed in the SAMA5D3x-MB MotherBoard documentation.

However, RedBoot can be used to provide development support. RedBoot provides gdb stub functionality. so it is then possible to download and debug stand-alone and eCos applications via the gdb debugger. This can happen over either a serial line or over Ethernet. The RedBoot image can be a ROM application programmed into the parallel NOR flash, or a ROMRAM application loaded via the second-level bootloader. See RedBoot Location for an overview.

The bootstrap options for the SAMA5D3x parts are documented in the CPU variant documentation. How the CPU boots depends on the BMS signal (supplied by the motherboard via the CPU Module main connector pin 184). The CM has a Pull-Up on the CPU BMS pin so will default to BMS_BIT=0.

Note: The Embest/Flextronics CM is pre-installed with example application software. The software execute depends on the setting of CM jumper JP1. When JP1 is open then the NAND based AT91Bootstrap second-level boot loader is loaded into SRAM and used to start a NAND stored application world. When JP1 is closed then a system “test” application is loaded into SRAM from the SPI Dataflash and executed.

Warning

When JP1 is closed, if the example Atmel code is present and the NOR test (single test 05) is executed then it will erase the first 384K of the NOR flash (0x10000000..0x1005FFFF). This could erase any ROM application (e.g. RedBoot) that the user may have installed into the parallel NOR flash.

2017-02-09
Documentation license for this page: eCosPro License