Overview

Name

eCos Support for the MPC8309KIT Board -- Overview

Description

This document covers the MPC8309KIT board. The board consists of a MPC8309SOM card plugged in to a MPC830X carrier board. The SOM contains an MPC8309 microprocessor, 256MiB of RAM and 8MiB of Flash. There are external connections for a single RS232 UART and the Fast Ethernet Controller.

For typical eCos development, a RedBoot image is programmed into the flash memory, and the board will boot this image from reset. RedBoot provides gdb stub functionality so it is then possible to download and debug stand-alone and eCos applications via the gdb debugger using the serial line or Ethernet.

Supported Hardware

The Flash memory consists of 127 blocks each of 64KiB, and 8 blocks of 8KiB, occupying 8MiB. In a typical setup, RedBoot is programmed into the base of flash at 0xFE000000 and occupies the next 768KiB. The topmost 64KiB block is used to manage the flash and holds RedBoot fconfig values. The remainder may be used by application code.

There is a serial driver CYGPKG_IO_SERIAL_GENERIC_16X5X which supports the 16X5X compatible DUARTs. The package CYGPKG_IO_SERIAL_POWERPC_MPC8309KIT provides definitions to configure the generic driver to the board. Only UART0 is actually brought out to a usable DB9 external connector via an RS232 transceiver; UART1 is delivered to the second DB9 via an RS485 transceiver. This device can be used by RedBoot for communication with the host. The serial driver package is loaded automatically when configuring for the MPC8309KIT target.

The UEC Ethernet driver, CYGPKG_DEVS_ETH_POWERPC_UEC is used to control the QUICC Engine UCC based Ethernet device. This driver only supports a single Ethernet interface at present: the RJ-45 socket on the SOM board.

eCos manages the on-chip interrupt controller. The architecture-defined decrementer is used to implement the eCos system clock and the microsecond delay function. A GTM is used to implement a profiling timer. Other on-chip devices (Caches, GPIO, UARTs) are initialized only as far as is necessary for eCos to run. The remaining devices (PCI, CAN, USB etc.) are not touched.

Interrupt Nesting

eCos normally operates with a sequential interrupt model, where each ISR is run with interrupts disabled and coincident ISRs are run in turn. However, the PowerPC HAL and kernel are designed to support nested interrupts where required. The MPC83XX variant HAL and MPC8309KIT platform HAL have been validated for nested interrupt support.

No special configuration is required to use nested interrupts, support for this is always present. Nested interrupts can be enabled simply by re-enabling interrupts in an ISR. However, there are a number of issues that need to be considered:

  1. All ISRs are entered with interrupts disabled and should be exited with interrupts disabled. So the ISR must bracket any code that can be preempted with enable and disable calls.

  2. An ISR must cancel the cause of its own interrupt before re-enabling interrupts otherwise it could put the CPU into an interrupt loop. This should include a call to cyg_interrupt_acknowledge(), maybe writing to device registers, or even a call to cyg_interrupt_mask() to block the interrupt source.

  3. Stack usage within ISRs and the level of nesting may require the value of CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE to be increased. Note that DSRs are also run on the interrupt stack, so excessive stack usage in any DSR must also be accounted for.

  4. ISRs for standard devices do not enable interrupts, and will thus run to completion with interrupts off. These ISRs will impose latency on the start of any nested ISR and will preempt it while interrupts are enabled. However, the only ISRs currently supported are for the Ethernet, serial, I2C and system timer, all of which are either minimal, or very simple.

  5. There is no prioritisation of ISRs, hardware prioritisation only determines which of any simultaneously pending ISRs is delivered to the CPU next. Any ISR can interrupt any other, low priority ISRs are not blocked by high priority ones. If some sort of prioritisation is required, it must be implemented in software by selectively masking and unmasking vectors as appropriate.

The following shows the suggested layout of an ISR that supports nesting:

    cyg_uint32 nested_isr( cyg_uint32 vector, CYG_ADDRWORD data )
    {
        CYG_INTERRUPT_STATE ints;

        cyg_interrupt_acknowledge( vector );

        // Cancel or mask interrupt here

        // Enable CPU interrupts
        HAL_ENABLE_INTERRUPTS();

        // Code here is preemptable

        // Disable interrupts before return
        HAL_DISABLE_INTERRUPTS(ints);

        return 1;
    }
   

See the Timers Test for an example of a program that uses nested interrupts.

Tools

The MPC8309KIT port is intended to work with GNU tools configured for a powerpc-eabi target. The original port was undertaken using powerpc-eabi-gcc version 4.4.5, powerpc-eabi-gdb version 7.2, and binutils version 2.20.1.

2017-02-09
Documentation license for this page: eCosPro License