Test Programs

Name

Test Programs -- Details

Test Programs

The MPC8309KIT HAL contains some test programs which allow various aspects of the microcontroller or the architecture to be tested.

Timers Test

The timers test checks the functionality of the microcontroller timers and in particular the interrupt nesting mechanism. This test also acts as and example of how to handle nested interrupts. The test programs the four available GTM timers to interrupt at a variety of different rates and records various parameters. The timers are programmed to interrupt at higher rates for higher interrupt priority timers. This information is summarized at the start of the run:

Options:
	LOOPS        24
	LOITER       1
	DSRS         1
	MHZ          10
	SYSTICK      1
	DELAY        0
	LATENCY      1
	LATENCY_HIST 20
	LATENCY_BASE 0

	CSB clock    133333332Hz

T  Interval Frequency    Tick Prescaler Vector
4:    127us  10256410    97ns        13     73
2:    355us  10256410    97ns        13     79
3:    731us  10256410    97ns        13     85
1:    999us  10256410    97ns        13     91
   

The options indicate what compile-time options have been applied. See the source of the test for a brief description of each. The table gives for each timer the requested interval between interrupts, the programmed frequency, the resulting length of a tick, the prescaler used to achieve this and the interrupt vector. Each timer is programmed to run at approximately 10MHz and the tick value is the resulting tick duration at that frequency. Each timer will actually interrupt every Interval*Tick*MHZ nanoseconds. The vector numbers also define the static priority of the interrupts, so timer 4 is highest priority, and timer 1 lowest. After initialization the test outputs a sequence of tables of the following format every 5 seconds:

ISRs max_nesting 5 max_nesting_seen 6
Spurious interrupts: 0

ISR Preempt:
T  Ticks    0    1    2    3    4
4:  944k 688k  81k  89k  84k   66
2:  338k 245k  28k    0  29k  34k
3:  164k 118k  13k  15k    0  16k
1:  120k  86k    0  10k  10k  12k
ISR Nesting:
T      1    2    3    4    5    6
4:  688k 204k  43k 6810  966    0
2:  245k  73k  16k 1991   63    0
3:  118k  36k 8144 1002   24    2
1:   86k  26k 5975  792    4    1
DSRs
T:               0    1    2    3    4
4:  preempt:  671k 5522 5524 5510  369
      count:     0  93k  317    0    0
2:  preempt:  239k 1933    2 1973 1969
      count:     0  33k    0    0    0
3:  preempt:  115k  955 1063    0  955
      count:     0  16k    0    0    0
1:  preempt:   84k    0  711  689  691
      count:     0  12k    0    0    0
ISR Latency
 T:  Max  Ave  Histogram (ns)...
      ns   ns    0   97  194  291  388  485  582  679  776  873  970 1067 1164 1261 1358 1455 1552 1649 1746 1843+
 4: 1455  485    0    0  261  466  496 700k 233k 2644 1150 1037  941  889  875  714  355  194    1    2    0   61
 2: 1649  485    0    0   79   84   75 248k  81k 1200  784  751  672  577  626  609  550  388  261 1083    9   73
 3: 1649  485    0    0   16   15   20 120k  38k  620  397  396  368  352  343  329  319  243  182  721    8   60
 1: 2716  485    0    0    0    0    0  87k  28k  515  293  293  263  252  275  253  252  200  145  576   14   59
   

The first line shows the depth of ISR nesting seen since the last report, plus the maximum seen throughout the run. The second line counts the number of spurious interrupts seen, and should always be zero. The above example is taken from the end of a run, although there are only 4 timers, this run has seen a nesting level of 5 and a whole run total of 6.

The ISR Preempt table contains a row for each timer. The Ticks column shows the total number of ISRs called for this timer. The 0 column shows how many ISR calls interrupted thread state. The remaining columns show how many ISR calls preempted the ISR for the given timer. For example, the ISR for timer 3 preempted the ISR for timer 2 about 15000 times. Mostly the ISRs do not interrupt themselves, but timer 4's ISR has interrupted itself 66 times. This is because the ISRs delay for a while to improve the possibility of preemption, and the accumulation of latencies occasionally results in an ISR still running when the next interrupt occurs. Note that this only records the ISR immediately below the current one on the stack, not every nested ISR.

The ISR Nesting table indicates for each ISR how deeply nested the ISRs are when each is run. In each line, the 1 column indicates how many times the ISR was first on the stack, the 2 column how many times there was one preempted ISR, the 3 column how many times there were two preempted ISRs and so on. For example, the ISR for timer 1 has been at the base of the stack about 86000 times, preempted one other ISR about 26000 times and preempted a stack of five ISRs just once.

The DSRs table contains two rows for each timer. The preempt: row shows how many times the ISR preempted the DSR for the given timer. The zero column correspond to thread state as before. For example the ISR for timer 2 preempted the DSR for timer 4 1969 times. The count: row shows the range of count values passed to the DSR and indicates the number of DSR calls not matched exactly to ISR calls. The ISR calls the DSR every 10 ticks, so the total counts should be one tenth of the ISR Ticks value. In this run only timer 4 has accumulated any instances where a new ISR occurred before a previously posted DSR could run.

The ISR latency table shows, for each ISR the range of ISR latencies. This is done by reading the timer counter on entry to the ISR and calculating the delay from the point at which the timer triggered the interrupt. For each timer the maximum latency seen is recorded, together with the average for the last 5 seconds. In the histogram, each column represents an additional tick of the 10MHz frequency of each timer, multiplied up to its duration in nanoseconds. Entries count the number of ISRs that were seen with that latency and the 1843+ column accumulates all larger latencies.

I2C Tests

Two programs are supplied to test the functioning of I2C. The MPC8309KIT board has a number of I2C devices, but no external access to the busses. These tests access the only device that provides visible confirmation of its functions: by manipulating the LEDs attached to a PCA9534 GPIO expander on the carrier board on I2C bus 2.

There are two programs; pca9534_1 operates the I2C device in polled mode and pca9534_2 operates in in interrupt driven mode. Otherwise they are identical.

2017-02-09
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