-- eCos Support for the TSEplus Hardware Design on a Stratix II/2s60-RoHS Board
This package provides the hardware design HAL for the eCosPro TSEplus
hardware design running on a Stratix II/2s60-RoHS board. The
design is based on the TSE_SGDMA design provided with the Altera
Nios II Embedded Design Suite, with a number of extensions.
It includes the following functionality:
A Nios II/f processor running at 85MHz. This has 4K of
instruction cache and 2K of data cache. It has level 2 jtag support
with two hardware breakpoints. The reset vector is at address
0x00000000 in external flash and the exception vector is at address
0x04000020 in external SDRAM.
16MB of external AMD flash at 0x00000000 attached via an 8-bit data bus.
32MB of external SDRAM at 0x04000000.
2MB of external SRAM at 0x01200000.
8K of on-chip RAM at 0x01400000. Some of this will used by the triple
speed ethernet device driver to store DMA descriptors.
An Avalon timer labelled sys_clk used to implement
the main eCos system clock. This defaults to 100Hz but can be changed
via the CYGNUM_HAL_RTC_PERIOD eCos configuration option.
An Avalon uart connected to the external transceiver on the board.
This is hardwired to 8 bits, no parity, and 1 stop bit. The default
baud rate is 115200 but can be changed at run-time. The RTS and CTS
signals are supported. This uart is used by eCos for the HAL diagnostics
and debug channel.
A triple speed ethernet tse_mac and associated rx_sgdma and tx_sgdma
scatter-gather DMA controllers. This provides network communications
for RedBoot and for eCos applications using one of the available
TCP/IP stacks. Note that this device requires an external phy board to
be plugged into one of the main board's expansion connectors.
An interface to the external lan91c111 ethernet chip on the board.
This can be used for network communication instead of the triple speed
ethernet device, useful if the external phy board is not available.
An Avalon timer set up to act as a watchdog device with a 10-second
An additional Avalon timer used for gprof-based profiling.
GPIO units connected to the row of LEDs, the dual seven-segment
display, and the buttons. The devkit platform HAL provides some
utility functions for the first two of these.
A system id register. This is used by RedBoot to check that the
current hardware design matches the RedBoot build.
A number of other hardware units including a second Avalon timer, a
jtag uart, a character LCD controller, and an EPCS serial flash
controller. These are not currently used by eCos so can be accessed
directly by application code.
The TSEplus hardware design HAL package is used with two different
eCos targets. The nios2_stratix2_2s60_rohs_tseplus
target includes the TSE ethernet driver but not the lan91c111 ethernet
driver, and can be used when the external phy board is present. The
nios2_stratix2_2s60_rohs_lan91c111 target includes
the lan91c111 ethernet driver but no the TSE ethernet driver and can
be used in the absence of the external phy board. When using a RAM
startup configuration the same eCos target should be used for both
RedBoot and the application.
The hardware design HAL package will be loaded automatically when
creating an eCos configuration for either target, together with the
Nios II architectural HAL and the devkit platform HAL. It should
never be necessary to load this package explicitly. Unloading the
package should only happen as a side effect of switching target
hardware. The package does not contain any user configuration options.
The package contains a single configuration option,
CYGNUM_HAL_RTC_PERIOD. This determines the period
of the system clock. By default this operates at 100Hz but the value
can be changed if a faster or slower clock is desired. The value is
used to program the PERIODH and
PERIODL registers of the
sys_clk Avalon timer.
For typical eCos usage the memory map is as follows: