Cyclone II TSEplus Hardware Design HAL

Name

Overview -- eCos Support for the TSEplus Hardware Design on a Cyclone II/2c35 Board

Description

This package provides the hardware design HAL for the eCosPro TSEplus hardware design running on a Cyclone II/2c35 board. The design is based on the TSE_SGDMA design provided with the Altera Nios II Embedded Design Suite, with a number of extensions. It includes the following functionality:

CPU

A Nios II/f processor running at 85MHz. This has 4K of instruction cache and 2K of data cache. It has level 2 jtag support with two hardware breakpoints. The reset vector is at address 0x00000000 in external flash and the exception vector is at address 0x04000020 in external SDRAM.

Flash

16MB of external AMD flash at 0x00000000 attached via an 8-bit data bus.

SDRAM

32MB of external SDRAM at 0x04000000.

SRAM

2MB of external SRAM at 0x01200000.

IRAM

8K of on-chip RAM at 0x01400000. Some of this will used by the triple speed ethernet device driver to store DMA descriptors.

system clock

An Avalon timer labelled sys_clk used to implement the main eCos system clock. This defaults to 100Hz but can be changed via the CYGNUM_HAL_RTC_PERIOD eCos configuration option.

uart

An Avalon uart connected to the external transceiver on the board. This is hardwired to 8 bits, no parity, and 1 stop bit. The default baud rate is 115200 but can be changed at run-time. The RTS and CTS signals are supported. This uart is used by eCos for the HAL diagnostics and debug channel.

TSE

A triple speed ethernet tse_mac and associated rx_sgdma and tx_sgdma scatter-gather DMA controllers. This provides network communications for RedBoot and for eCos applications using one of the available TCP/IP stacks. Note that this device requires an external phy board to be plugged into one of the main board's expansion connectors.

lan91c111

An interface to the external lan91c111 ethernet chip on the board. This can be used for network communication instead of the triple speed ethernet device, useful if the external phy board is not available.

watchdog

An Avalon timer set up to act as a watchdog device with a 10-second timeout.

profiling

An additional Avalon timer used for gprof-based profiling.

GPIO

GPIO units connected to the row of LEDs, the dual seven-segment display, and the buttons. The devkit platform HAL provides some utility functions for the first two of these.

sysid

A system id register. This is used by RedBoot to check that the current hardware design matches the RedBoot build.

Other

A number of other hardware units including a second Avalon timer, a jtag uart, a character LCD controller, and an EPCS serial flash controller. These are not currently used by eCos so can be accessed directly by application code.

Configuration Options

The TSEplus hardware design HAL package is used with two different eCos targets. The nios2_cyclone2_2c35_tseplus target includes the TSE ethernet driver but not the lan91c111 ethernet driver, and can be used when the external phy board is present. The nios2_cyclone2_2c35_lan91c111 target includes the lan91c111 ethernet driver but no the TSE ethernet driver and can be used in the absence of the external phy board. When using a RAM startup configuration the same eCos target should be used for both RedBoot and the application.

The hardware design HAL package will be loaded automatically when creating an eCos configuration for either target, together with the Nios II architectural HAL and the devkit platform HAL. It should never be necessary to load this package explicitly. Unloading the package should only happen as a side effect of switching target hardware. The package does not contain any user configuration options.

The package contains a single configuration option, CYGNUM_HAL_RTC_PERIOD. This determines the period of the system clock. By default this operates at 100Hz but the value can be changed if a faster or slower clock is desired. The value is used to program the PERIODH and PERIODL registers of the sys_clk Avalon timer.

Memory Map

For typical eCos usage the memory map is as follows:

AddressPurpose
0x0000000016MB of flash
0x00000000reset vector
0x00000000128K for RedBoot code
0x00800000current hardware design
0x00c00000factory hardware design
0x00FF0000RedBoot fis and fconfig data
0x012000002MB of SRAM
0x014000008K of on-chip IRAM
0x01401E00TSE DMA descriptors
0x01403000peripherals
0x0400000032MB of SDRAM
0x04000020exception vector
0x04000100~64K for RedBoot data
0x04010000application code and data

2017-02-09
Documentation license for this page: eCosPro License