STPC Atlas Processor

Name

CYGPKG_HAL_I386_STPC_ATLAS -- eCos Support for the STPC Atlas Processor

Description

The STPC Atlas is an x86 core PC compatible system-on-chip intended for embedded applications. The central processor is largely 486-compatible and can run at up to 133MHz. The chip includes an integrated SDRAM controller, a VGA/SVGA graphics controller with TFT panel support, two serial ports, a parallel port, keyboard, mouse and USB host interfaces, support for PCI, PCMCIA and ISA buses as well as a local bus, and interrupt controller, timers, and DMA engines as per the standard PC architecture.

The STPC Atlas variant HAL package CYGPKG_HAL_I386_STPC_ATLAS provides support for all platforms based around this chip. It complements the I386 architectural HAL CYGPKG_HAL_I386. An eCos configuration for an STPC Atlas-based platform should also include a platform HAL package to support board-level details like the nature of the external memory chips.

Configuration

The STPC Atlas variant HAL package should be loaded automatically when eCos is configured for appropriate target hardware. It should never be necessary to load this package explicitly. Unloading the package should only happen as a side effect of switching target hardware.

The package does not contain any configuration options.

The HAL Port

This section describes how the STPC Atlas variant HAL package implements parts of the eCos HAL specification. It should be read in conjunction with similar sections from the architectural and platform HAL documentation.

HAL I/O

The cyg/hal/var_io.h header provides definitions for the on-chip peripherals. This header file is automatically included by the architectural cyg/hal/hal_io.h so other packages and application code will usually only include the latter. It is also necessary to include cyg/hal/hal_intr.h. The definitions largely follow the STPC documentation, so for example the ISA Port_B register has a definition HAL_STPC_ATLAS_Port_B, and there also definitions HAL_STPC_ATLAS_Port_B_PE and HAL_STPC_ATLAS_Port_B_SE for the PE and SE bits.

STPC Atlas registers can be accessed in a variety of ways. Some of them can be accessed directly via the x86 in and out instructions, and the eCos macros HAL_READ_UINT8, HAL_WRITE_UINT8, etc. can be used for these. However there are also memory-mapped registers, registers accessed indirectly via the IDX and DATA registers, local bus registers, PCI registers, and so on. In an attempt to reduce confusion various suffixes are used, and in some cases utility macros are provided to access the registers:

TypeSuffixSizeAccess using
Normal I/O portNone8, 16 or 32HAL_READ_UINT8, HAL_WRITE_UINT8 etc.
Indexed via 0x22/0x23_IDX8 bitsHAL_STPC_ATLAS_READ_IDX and HAL_STPC_ATLAS_WRITE_IDX
Host bus_HB32 bitsHAL_STPC_ATLAS_READ_HB and HAL_STPC_ATLAS_WRITE_HB
Local bus_LB16 bitsHAL_STPC_ATLAS_READ_LB and HAL_STPC_ATLAS_WRITE_LB
PC_PCI32 bitsHAL_STPC_ATLAS_READ_PCI and HAL_STPC_ATLAS_WRITE_PCI
PCMCIA_PCMCIA8 bitsHAL_STPC_ATLAS_READ_PCMCIA and HAL_STPC_ATLAS_WRITE_PCMCIA
Memory_MEM32 bitsas C pointers

Accessing IDX, HB, LB, PCI and PCMCIA registers involves non-atomic sequences of operations so to avoid concurrency problems the associated macros briefly disable interrupts. If this is known to be unnecessary, for example because the relevant code runs during system initialization before interrupts are enabled, then INTS_UNSAFE variants of the macros such as HAL_STPC_ATLAS_READ_IDX_INTS_UNSAFE can be used instead.

Interrupts

The STPC Atlas variant HAL provides default implementations of the HAL macros related to the interrupt controller: HAL_INTERRUPT_ACKNOWLEDGE, HAL_INTERRUPT_MASK, HAL_INTERRUPT_UNMASK, HAL_INTERRUPT_CONFIGURE and HAL_INTERRUPT_SET_LEVEL. The platform HAL can override these definitions if platform-specific macros are more appropriate. It is up to the platform HAL to define the interrupt vector numbers. The SET_LEVEL macro is a no-op so there is no support for prioritizing interrupts.

Clock and Profiling Support

The STPC Atlas variant HAL provides default definitions of the clock-related macros HAL_CLOCK_INITIALIZE, HAL_CLOCK_RESET, HAL_CLOCK_READ and HAL_CLOCK_LATENCY. The implementation uses the processor's PIT0 timer since that is the only on-chip timer which can generate interrupts. The platform HAL determines the default clock frequency, and can override any of these definitions if required. If the variant HAL clock macros should be used then the platform HAL should implement the CDL interface CYGINT_HAL_I386_STPC_ATLAS_STANDARD_CLOCK.

When the variant HAL's clock macros are enabled the package will also provide profiling timer support.

Idle Thread Processing

The variant HAL defines a macro HAL_IDLE_THREAD_ACTION which gets invoked automatically by the kernel's idle thread. This macro executes a hlt instruction, suspending the CPU until the next interrupt and thus reducing power consumption. The platform HAL can override this definition if necessary.

Other Functionality

The variant HAL defines a HAL_PLATFORM_RESET macro which resets the processor using functionality provided by the STPC Atlas' keyboard/mouse controller. It also provides a HAL_DELAY_US macro which works in terms of a simple busy loop, so it does not depend on PIT0 having been started.

The implementation of other parts of the HAL specification is unaffected, and no additional functionality is provided.

2017-02-09
Documentation license for this page: eCosPro License