Pin Configuration and GPIO Support

Name

Pin Configuration and GPIO Support -- Use of pin configuration and GPIO

Synopsis

#include <cyg/hal/hal_io.h>    
    

pin = CYGHWR_HAL_L1XX_PINMUX(reg, field, func);

CYGHWR_HAL_L1XX_PINMUX_SET(pin);

pin = CYGHWR_HAL_L1XX_GPIO(bank, bit, mode);

CYGHWR_HAL_L1XX_GPIO_SET(pin);

CYGHWR_HAL_L1XX_GPIO_OUT(pin, val);

CYGHWR_HAL_L1XX_GPIO_IN(pin, val);

CYGHWR_HAL_L1XX_GPIO_INTCFG(pin, mode);

CYGHWR_HAL_L1XX_GPIO_INTSTAT(pin, stat);

Description

The OMAP L1XX HAL provides a number of macros to support the encoding of pin multiplexing information and GPIO pin modes into 32 bit descriptors. This is useful to drivers and other packages that need to configure and use different lines for different devices. Because there is not a simple correspondence between pin multiplexing information and GPIO bank and pin identities, these two things are treated separately.

Pin Multiplexing

A pin multiplexing descriptor is created with CYGHWR_HAL_L1XX_PINMUX( reg, field, func ) which takes the following arguments:

reg

This identifies the PINMUX register which controls this pin. This is a value between 0 and 19.

field

This gives the bit offset within the PINMUX register of the field that controls this pin. Fields are 4 bits wide, so this may only be 0, 4, 8, 12, 16, 20, 24 or 28.

func

This defines the function code to program into the PINMUX field. There is no consistency between functions and function codes, and the same function for a pin may be represented by different codes in different PINMUX registers. You should refer to the OMAP L1xx documentation for the correct value to be used here.

The following examples show how this macro may be used:

// UART0 TX line is in PINMUX3, bits 20:23, function 2 = UART0_TXD    
#define CYGHWR_HAL_L1XX_UART0_TX             CYGHWR_HAL_L1XX_PINMUX( 3, 20, 2 )

// MMCSS0 clock line is in PINMUX10, bits 0:3, function 2 = MMCSD0_CLK    
#define CYGHWR_HAL_OMAP_MMCSD0_CLK                      CYGHWR_HAL_L1XX_PINMUX( 10,  0, 2 )
   

The macro CYGHWR_HAL_L1XX_PINMUX_SET( pin ) sets the pin multiplexing setting according to the descriptor passed in.

GPIO Support

A GPIO descriptor is created with CYGHWR_HAL_L1XX_GPIO( bank, bit, mode) which takes the following arguments:

bank

This identifies the GPIO bank to which the pin is attached. This is a value between 0 and 7.

bit

This gives the bit offset within the bank of the GPIO pin. This is a value between 0 and 15.

mode

This defines whether this is an input or an output pin, and may take the values INPUT or OUTPUT respectively.

Additionally, the macro CYGHWR_HAL_L1XX_GPIO_NONE may be used in place of a pin descriptor and has a value that no valid descriptor can take. It may therefore be used as a placeholder where no GPIO pin is present or to be used.

The following examples show how this macro may be used:

// MMCSD0 card detect is attached to GP4[0] and is an input    
#define CYGHWR_HAL_OMAP_MMCSD0_CD_GPIO                  CYGHWR_HAL_L1XX_GPIO( 4, 0, INPUT )

// MMCSD0 write protect is attached to GP4[1] and is an input        
#define CYGHWR_HAL_OMAP_MMCSD0_WP_GPIO                  CYGHWR_HAL_L1XX_GPIO( 4, 1, INPUT )
   

The remaining macros all take a GPIO pin descriptor as an argument. CYGHWR_HAL_L1XX_GPIO_SET configures the pin according to the descriptor and must be called before any other macros. CYGHWR_HAL_L1XX_GPIO_OUT sets the output to the value of the least significant bit of the val argument. The val argument of CYGHWR_HAL_L1XX_GPIO_IN should be a pointer to an int, which will be set to 0 if the pin input is zero, and 1 otherwise.

There is also support for GPIO interrupts. CYGHWR_HAL_L1XX_GPIO_INTCFG( pin, mode ) configures the interrupt mode of the pin. It may be either FALL, RISE or FALLRISE to configure the pin to interrupt on the falling edge, rising edge or both. The second argument to CYGHWR_HAL_L1XX_GPIO_INTSTAT( pin, stat ) must be a pointer to an int, which will be set to 1 if an interrupt has be received on the given pin, and 0 otherwise. GPIO interrupts are currently not decoded into per-pin interrupt vectors, only the shared per-bank vectors are available. If an application needs to get interrupts from more than one pin on a bank, it needs to install a shared ISR and decode the specific pins itself.

2017-02-09
Documentation license for this page: eCosPro License