Cortex-M Architectural HAL


CYGPKG_HAL_CORTEXM -- eCos Support for the Cortex-M Architecture


The Cortex-M implements a new version of the ARM architecture intended for deeply embedded applications. The processor runs the Thumb-2 instruction set and implements an exception and interrupt model quite different from that supported by previous members of the ARM architecture. For this reason the Cortex-M HAL is implemented as an entirely new architecture within eCos.

In addition to the processor, the Cortex-M architecture also provides definitions of a Nested Vectored Interrupt Controller (NVIC) and a system tick timer. Both of these are used by eCos. If available on the target platform, and when suitably configured, the eCos Cortex-M HAL can make use of the Instrumentation Trace Macrocell (ITM) for diagnostics and instrumentation. Other features of the architecture such as the Memory Protection Unit, and the other debug units are not directly used by eCos at present.

Documentation license for this page: eCosPro License