Setup

Name

Setup -- Preparing the TWR-K70F120M Board for eCos Development

Overview

Since the target motherboard provides a built-in hardware debug solution, it is expected that the most common development method when targeting the CPU is to use this hardware debug interface for development. This will either be by loading smaller applications into on-chip SRAM, or by programming larger applications directly into on-chip flash. In the first case, eCos applications should be configured for the variant JTAG startup type, and in the second case for the variant ROM startup type. Since the TWR-K70F120M motherboard provides 128MB of external SDRAM it is also possible to configure larger applications for hardware debug using that external memory using the platform JTAG startup type.

Note: When using the platform JTAG startup type to load application programs into the external SDRAM the host hardware debugger configuration is responsible for initialising the necessary CPU I/O to allow GDB to load the application into SDRAM.

HAL Startup Types

For the twr_k70f120m platform the Kinetis variant HAL support provides some common startup types, which are extended by the platform HAL. The following variant HAL provided startup types may be selected for applications:

ConfigurationDescription
ROMStand-alone programs running from internal FLASH
SRAMPrograms loading via hardware debugger into on-chip SRAM, but expecting RedBoot or GDB stub ROM
RAMCurrently not supported: Programs loading via RedBoot or GDB stub ROM into on-chip SRAM
JTAGStand-alone programs running from on-chip SRAM, loaded via hardware debugger

The following TWR-K70F120M platform specific startup types may also be selected for applications:

ConfigurationDescription
ByVariantThe variant defines the startup configuration
ROMStand-alone programs running from internal FLASH
RAMCurrently not supported: Programs loading via RedBoot or GDB stub ROM into off-chip SDRAM
JTAGStand-alone programs running from off-chip SDRAM, loaded via hardware debugger

Further details are available later in this manual.

Preparing OSJTAG interface

The support for using the on-chip OSJTAG interface for hardware debugging and diagnostic output requires that the OSJTAG firmware is at least version v30.21. The firmware for the OSJTAG interface can be checked, and updated if needed, using the relevant firmware updater tool available for download via the Freescale website. Unfortunately the official firmware updater is only available for the Windows platform at the moment.

Programming ROM images

To program ROM startup applications into flash a hardware debugger that understands the Kinetis flash may be used. For example, the Ronetix PEEDI provides suitable support.

Warning

Due to a security feature of the Kinetis CPUs care should be taken to avoid completely erasing the flash to ensure the required FSEC value in the flash configuration field is not lost. For example when using the PEEDI the user should NOT use the “erase” suffix to the flash program command. The Kinetis aware flash erase chip should be executed to erase the flash prior to using the flash program command.

Programming ROM images with a Ronetix PEEDI

This section describes how to program ROM images using a Ronetix PEEDI debugger.

The PEEDI must be configured to allow communication with your local network, and configured with the parameters for interfacing with the target board. It must then be used to download and program the ROM image into the internal flash. The following steps give a typical outline for doing this. Consult the PEEDI documentation for alternative approaches, such as using FTP or HTTP instead of TFTP.

Preparing the Ronetix PEEDI JTAG debugger

  1. Prepare a PC to act as a host and start a TFTP server on it.

  2. Connect the PEEDI JTAG debugger via both serial and ethernet to the host PC and power it on. Use the serial cable supplied with the PEEDI (straight through, not null modem).

  3. Verify the PEEDI is using up-to-date firmware, of version 12.3.0 or later. Older PEEDI firmware does not support the Kinetis family correctly, particularly if wishing to use the PEEDI's own 'flash' commands to modify the on-chip flash. If the firmware is not recent enough, follow the PEEDI User Manual's instructions which describe how to update the PEEDI firmware.

  4. Locate the PEEDI configuration file peedi_twr_k70f120m.cfg within the eCos platform HAL package in the source repository. This will be in the directory packages/hal/cortexm/kinetis/twr_k70f120m/VERSION/misc relative to the root of your eCos installation.

  5. Place the PEEDI configuration file in a location on the PC accessible to the TFTP server. Later you will configure the PEEDI to load this file via TFTP as its configuration file.

  6. Open peedi_twr_k70f120m.cfg in an editor such as emacs or notepad and insert your own license information in the [LICENSE] section.

  7. Install and configure the PEEDI in line with the PEEDI Quick Start Guide or User's Manual, especially configuring PEEDI's RedBoot with the network information. Configure it to use the peedi_twr_k70f120m.cfg target configuration file on the TFTP server at the appropriate point of the config process, for example with a path such as: tftp://192.168.7.9/peedi_twr_k70f120m.cfg

  8. Reset the PEEDI.

  9. Connect to the PEEDI's CLI interface via TCP/IP on the standard telnet port 23. The telnet application is suitable for this. You should see output similar to the following:

    $ telnet 192.168.7.225
    Trying 192.168.7.225...
    Connected to 192.168.7.225.
    Escape character is '^]'.
    
    PEEDI - Powerful Embedded Ethernet Debug Interface
    Copyright (c) 2005-2011 www.ronetix.at - All rights reserved
    Hw:1.2, L:JTAG v1.6 Fw:13.3.0, SN: PD-XXXX-XXXX-XXXX
    ------------------------------------------------------------
    
    twr_k70f120m>
            

Preparing the TWR-K70F120M board for programming with PEEDI

Follow the steps in this section in order to allow communication between the board and the host PC, and between the board and the PEEDI device.

If programming an application which uses serial output, you should first:

  1. If OSJTAG firmware 30.21 or later is installed then the motherboard J13 USB provides a standard CDC-ACM virtual serial connection to the host computer. The alternative is to connect a null modem cable between the DB9 RS232 connector on the TWR-SER daughterboard and the host computer.

  2. Start a suitable terminal emulator on the host computer such as minicom on Linux or PuTTY on Windows. Set the communication parameters to 38400 baud, 8 data bits, no parity bit and 1 stop bit with no flow control.

For all applications, you must:

  1. Connect the board to the PEEDI using an appropriate 20-pin cable from the JTAG interface connector to the Target port on the PEEDI. This will normally be a PEEDI-CORTEX20 adapter.

  2. Power up the TWR-K70F120M board.

  3. Connect to the PEEDI's telnet CLI on port 23 as before.

  4. Confirm correct connection with the PEEDI with the reset reset command as follows:

    twr_k70f120m> reset reset
    ++ info: user reset
    twr_k70f120m> 
    ++ info: RESET and TRST asserted
    ++ info: TRST released
    ++ info: TAP : IDCODE = 0x2BA01477, Cortex M3 SWD
    ++ info: RESET released
    ++ info: core connected
    
    CORE0 -> CortexM4 - stopped by breakpoint
             PC=0x1FFF0006, xPSR=0x01000000
    
    core #0 stopped
    ++ info: core 0: initialized
    
    twr_k70f120m>
             

Installation into flash

The following describes the procedure for installing a ROM application into on-chip flash, using the GDB stub ROM image as an example of such an application.

  1. Use arm-eabi-objcopy to convert the linked application, in ELF format, into binary format. For example:

    $ arm-eabi-objcopy -O binary programname programname.bin
            

  2. Copy the binary file (.bin file) into a location on the host computer accessible to its TFTP server.

  3. Connect to the PEEDI's telnet interface, and program the image into flash with the following commands, replacing TFTP_SERVER with the address of the TFTP server and /BINPATH with the location of the .bin file relative to the TFTP server root directory. For example for a RedBoot ROM image:

    twr_k70f120m> flash erase chip
    
    erasing chip at 0x00000000 
    done.
    
    ++ info: successfully erased 1 byte in 0.33 sec
    
    twr_k70f120m> flash program tftp://TFTP_SERVER/BINPATH/redboot.bin bin 0x00000000
    ++ info: Programming image file: tftp://TFTP_SERVER/redboot.bin
    ++ info: Programming directly
    ++ info: At absolute address:    0x00000000
    programming at 0x00000000
    programming at 0x00001000
    programming at 0x00002000
    programming at 0x00003000
    programming at 0x00004000
    programming at 0x00005000
    programming at 0x00006000
    programming at 0x00007000
    programming at 0x00008000
    programming at 0x00009000
    programming at 0x0000A000
    programming at 0x0000B000
    programming at 0x0000C000
    programming at 0x0000D000
    programming at 0x0000E000
    programming at 0x0000F000
    programming at 0x00010000
    programming at 0x00011000
    programming at 0x00012000
    programming at 0x00013000
    programming at 0x00014000
    programming at 0x00015000
    
    ++ info: successfully programmed 88.00 KB in 0.74 sec
    
    twr_k70f120m>
            

The installation into flash is now complete. For applications which print output on startup to the USART3 RS232 serial port, such as the GDB stub ROM application, this can easily by tested by powering off the board, disconnecting the JTAG, and then powering on the board again. In the case of the GDB stub ROM image, output similar to the following should be visible (although specific numbers may differ):

$T050f:72250008;0d:f0ff0120;#8a
      

RedBoot

RedBoot is currently unsupported.

2017-02-09
Documentation license for this page: eCosPro License