The HAL Port

Name

HAL Port -- Implementation Details

Overview

This documentation explains how the eCos HAL specification has been mapped onto the STM32X0G-EVAL board hardware, and should be read in conjunction with that specification. The STM32X0G-EVAL platform HAL package complements the Cortex-M architectural HAL and the STM32 variant HAL. It provides functionality which is specific to the target board.

Startup

Following a hard or soft reset the HAL will initialize or reinitialize many of the on-chip peripherals. There is an exception for RAM startup applications which depend on a ROM monitor for certain services.

For ROM and JTAG startup, the HAL will perform additional initialization, programming the various internal registers including the PLL, peripheral clocks and GPIO pins. The details of the early hardware startup may be found in the src/stm32x0g_eval_misc.c in both hal_system_init and hal_platform_init.

Memory Map

The platform HAL package provides the memory layout information needed to generate the linker script. The key memory locations are as follows:

External RAM

This is located at address 0x64000000 of the memory space, and is 1MiB long. For ROM applications, all of RAM is available for use. For RAM startup applications, RAM below 0x64008000 is reserved for RedBoot and the top CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE bytes are reserved for the interrupt stack, the remainder is available for the application.

Internal RAM

This is located at address 0x20000000 of the memory space, and is 128KiB in size. On the STM3220G, the eCos VSR table occupies the bottom 388 bytes, with the virtual vector table starting at 0x20000184 and extending to 0x20000284. On the STM3240G, the eCos VSR table occupies the bottom 392 bytes on the STM3220G, with the virtual vector table starting at 0x20000188 and extending to 0x20000288. For ROM, ROMINT, SRAM and JTAG startups, the top CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE bytes are reserved for the interrupt stack. The remainder of internal RAM is available for use by applications.

The STM32F407IG based systems have a block of (close-coupled) SRAM located at address 0x10000000 of the memory space, and 64KiB in size.

Internal FLASH

This is located at address 0x08000000 of the memory space and will be mapped to 0x00000000 at reset. This region is 1024KiB in size. ROM applications are by default configured to run from this memory. This memory is managed by RedBoot's FIS system.

On-Chip Peripherals

These are accessible at locations 0x40000000 and 0xE0000000 upwards. Descriptions of the contents can be found in the STM32 User Manual.

Linker Scripts

The platform linker scripts define the following symbols:

hal_vsr_table

This defines the location of the VSR table. This is set to 0x20000000 for all startup types, and space for either 97 (F2 processors) or 98 (F4 processors) entries is reserved.

hal_virtual_vector_table

This defines the location of the virtual vector table used to communicate between an ROM monitor and an eCos application. This is allocated right after the VSR table, at 0x20000184 (F2) or 0x20000188 (F4).

hal_interrupt_stack

This defines the location of the interrupt stack. For ROM and JTAG startups, this is allocated to the top of internal SRAM, 0x20020000. For RAM startups, it is allocated to the top of external SRAM, 0x64200000.

hal_startup_stack

This defines the location of the startup stack. For all startup types it is initially allocated at the half-way point of the interrupt stack.

Diagnostic LEDs

Four LEDs are fitted on the board for diagnostic purposes: LED1 (green), marked as LD1; LED2 (orange) marked as LD2; LED3 (red) marked as LD3; and LED4 (blue) marked as LD4.

The platform HAL header file at <cyg/hal/plf_io.h> defines the following convenience function to allow the LEDs to be set:

       extern void hal_stm32x0_led(char c);
     
The lowest 4 bits of the argument c correspond to each of the 4 LEDs (with LED1 as the least significant bit).

The platform HAL will automatically light LED1 when the platform initialisation is complete, however the LEDs are free for application use.

Flash wait states

The STM32X0G-EVAL platform HAL provides a configuration option to set the number of Flash read wait states to use: CYGNUM_HAL_CORTEXM_STM32_FLASH_WAIT_STATES. It is important to verify and if necessary update this value if changing the CPU clock (HCLK) frequency or CPU voltage. Consult the STM32 Flash programming manual (PM0059) for appropriate values for different clock speeds or voltages. The default of 3 reflects a supply voltage of 3.3V and HCLK of 120MHz.

Real-time characterization

The tm_basic kernel test gives statistics gathered about the real-time characterization and performance of the kernel. The sample output is shown here for information. The test was built for ROMINT startup, which provided the best performance as both code and data could remain on-chip.

            Startup, main stack : stack used   348 size  3920
             Startup : Idlethread stack used    84 size  2048

eCos Kernel Timings
Notes: all times are in microseconds (.000001) unless otherwise stated

Reading the hardware clock takes 0 'ticks' overhead
... this value will be factored out of all other measurements
Clock interrupt took    6.03 microseconds (6 raw clock ticks)

Testing parameters:
   Clock samples:            32
   Threads:                   5
   Thread switches:         128
   Mutexes:                  32
   Mailboxes:                32
   Semaphores:               32
   Scheduler operations:    128
   Counters:                 32
   Flags:                    32
   Alarms:                   32


                                 Confidence
     Ave     Min     Max     Var  Ave  Min  Function
  ======  ======  ======  ====== ========== ========
    4.20    4.00    5.00    0.32   80%  80% Create thread
    1.20    1.00    2.00    0.32   80%  80% Yield thread [all suspended]
    1.20    1.00    2.00    0.32   80%  80% Suspend [suspended] thread
    1.00    1.00    1.00    0.00  100% 100% Resume thread
    1.40    1.00    2.00    0.48   60%  60% Set priority
    0.40    0.00    1.00    0.48   60%  60% Get priority
    3.20    3.00    4.00    0.32   80%  80% Kill [suspended] thread
    1.20    1.00    2.00    0.32   80%  80% Yield [no other] thread
    2.00    2.00    2.00    0.00  100% 100% Resume [suspended low prio] thread
    1.00    1.00    1.00    0.00  100% 100% Resume [runnable low prio] thread
    1.20    1.00    2.00    0.32   80%  80% Suspend [runnable] thread
    1.00    1.00    1.00    0.00  100% 100% Yield [only low prio] thread
    1.00    1.00    1.00    0.00  100% 100% Suspend [runnable->not runnable]
    3.20    3.00    4.00    0.32   80%  80% Kill [runnable] thread
    2.40    2.00    3.00    0.48   60%  60% Destroy [dead] thread
    4.60    4.00    6.00    0.72   80%  60% Destroy [runnable] thread
    5.80    5.00    7.00    0.64   40%  40% Resume [high priority] thread
    2.16    2.00    4.00    0.27   85%  85% Thread switch

    0.40    0.00    1.00    0.48   60%  60% Scheduler lock
    1.00    1.00    1.00    0.00  100% 100% Scheduler unlock [0 threads]
    0.99    0.00    1.00    0.02   99%   0% Scheduler unlock [1 suspended]
    0.98    0.00    1.00    0.03   98%   1% Scheduler unlock [many suspended]
    0.98    0.00    1.00    0.05   97%   2% Scheduler unlock [many low prio]

    0.38    0.00    1.00    0.47   62%  62% Init mutex
    1.38    1.00    2.00    0.47   62%  62% Lock [unlocked] mutex
    1.53    1.00    2.00    0.50   53%  46% Unlock [locked] mutex
    1.28    1.00    2.00    0.40   71%  71% Trylock [unlocked] mutex
    1.13    1.00    2.00    0.22   87%  87% Trylock [locked] mutex
    0.41    0.00    1.00    0.48   59%  59% Destroy mutex
    7.66    7.00    8.00    0.45   65%  34% Unlock/Lock mutex

    0.44    0.00    1.00    0.49   56%  56% Create mbox
    0.22    0.00    1.00    0.34   78%  78% Peek [empty] mbox
    1.38    1.00    2.00    0.47   62%  62% Put [first] mbox
    0.22    0.00    1.00    0.34   78%  78% Peek [1 msg] mbox
    1.34    1.00    2.00    0.45   65%  65% Put [second] mbox
    0.31    0.00    1.00    0.43   68%  68% Peek [2 msgs] mbox
    1.44    1.00    2.00    0.49   56%  56% Get [first] mbox
    1.44    1.00    2.00    0.49   56%  56% Get [second] mbox
    1.22    1.00    2.00    0.34   78%  78% Tryput [first] mbox
    1.16    1.00    2.00    0.26   84%  84% Peek item [non-empty] mbox
    1.13    1.00    2.00    0.22   87%  87% Tryget [non-empty] mbox
    1.09    1.00    2.00    0.17   90%  90% Peek item [empty] mbox
    1.13    1.00    2.00    0.22   87%  87% Tryget [empty] mbox
    0.06    0.00    1.00    0.12   93%  93% Waiting to get mbox
    0.19    0.00    1.00    0.30   81%  81% Waiting to put mbox
    0.47    0.00    1.00    0.50   53%  53% Delete mbox
    5.00    5.00    5.00    0.00  100% 100% Put/Get mbox

    0.31    0.00    1.00    0.43   68%  68% Init semaphore
    1.06    1.00    2.00    0.12   93%  93% Post [0] semaphore
    1.31    1.00    2.00    0.43   68%  68% Wait [1] semaphore
    1.13    1.00    2.00    0.22   87%  87% Trywait [0] semaphore
    1.13    1.00    2.00    0.22   87%  87% Trywait [1] semaphore
    0.41    0.00    1.00    0.48   59%  59% Peek semaphore
    0.41    0.00    1.00    0.48   59%  59% Destroy semaphore
    4.22    4.00    5.00    0.34   78%  78% Post/Wait semaphore

    0.44    0.00    1.00    0.49   56%  56% Create counter
    0.31    0.00    1.00    0.43   68%  68% Get counter value
    0.19    0.00    1.00    0.30   81%  81% Set counter value
    1.28    1.00    2.00    0.40   71%  71% Tick counter
    0.28    0.00    1.00    0.40   71%  71% Delete counter

    0.34    0.00    1.00    0.45   65%  65% Init flag
    1.19    1.00    2.00    0.30   81%  81% Destroy flag
    1.06    1.00    2.00    0.12   93%  93% Mask bits in flag
    1.19    1.00    2.00    0.30   81%  81% Set bits in flag [no waiters]
    1.75    1.00    2.00    0.38   75%  25% Wait for flag [AND]
    1.72    1.00    2.00    0.40   71%  28% Wait for flag [OR]
    1.66    1.00    2.00    0.45   65%  34% Wait for flag [AND/CLR]
    2.00    2.00    2.00    0.00  100% 100% Wait for flag [OR/CLR]
    0.28    0.00    1.00    0.40   71%  71% Peek on flag

    0.63    0.00    1.00    0.47   62%  37% Create alarm
    1.78    1.00    2.00    0.34   78%  21% Initialize alarm
    1.03    1.00    2.00    0.06   96%  96% Disable alarm
    1.63    1.00    2.00    0.47   62%  37% Enable alarm
    1.22    1.00    2.00    0.34   78%  78% Delete alarm
    1.44    1.00    2.00    0.49   56%  56% Tick counter [1 alarm]
    8.22    8.00    9.00    0.34   78%  78% Tick counter [many alarms]
    2.38    2.00    3.00    0.47   62%  62% Tick & fire counter [1 alarm]
   40.66   40.00   41.00    0.45   65%  34% Tick & fire counters [>1 together]
    9.16    9.00   10.00    0.26   84%  84% Tick & fire counters [>1 separately]
    6.00    6.00    6.00    0.00  100% 100% Alarm latency [0 threads]
    5.45    5.00    6.00    0.49   55%  55% Alarm latency [2 threads]
    5.39    5.00    6.00    0.48   60%  60% Alarm latency [many threads]
   10.01   10.00   11.00    0.01   99%  99% Alarm -> thread resume latency

    0.00    0.00    0.00    0.00            Clock/interrupt latency

    2.23    1.00    3.00    0.00            Clock DSR latency

  224    224     224  (main stack:   877)  Thread stack used (1360 total)
           All done, main stack : stack used   877 size  3920
            All done : Idlethread stack used   172 size  2048

Timing complete - 29800 ms total

PASS:<Basic timing OK>
EXIT:<done>
    
2017-02-09
Documentation license for this page: eCosPro License