The HAL Port

Name

HAL Port -- Implementation Details

Overview

This documentation explains how the eCos HAL specification has been mapped onto the STM324X9I-EVAL board hardware, and should be read in conjunction with that specification. The STM324X9I-EVAL platform HAL package complements the Cortex-M architectural HAL and the STM32 variant HAL. It provides functionality which is specific to the target board.

Startup

Following a hard or soft reset the HAL will initialize or reinitialize many of the on-chip peripherals. There is an exception for RAM startup applications which depend on a ROM monitor for certain services.

For ROM, ROMINT, SRAM, JTAG and SRAMEXT startup types the HAL will perform additional initialization, programming the various internal registers including the PLL, peripheral clocks and GPIO pins. The details of the early hardware startup may be found in the src/stm324x9i_eval_misc.c in both hal_system_init and hal_platform_init.

Memory Map

The platform HAL package provides the memory layout information needed to generate the linker script. For all the STARTUP variations the top CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE bytes of the on-chip SRAM are reserved for the interrupt stack. The remainder of the internal SRAM is available for use by applications. The key memory locations are as follows:

Internal RAM

This is located at address 0x20000000 of the memory space, and is 192KiB in size. The eCos VSR table occupies the bottom 392 bytes of memory, with the virtual vector table starting at 0x200001AC and extending to 0x200002AC.

For all configurations there is also a block of (close-coupled) SRAM located at address 0x10000000 of the memory space, and 64KiB in size.

External SDRAM

This is located at address 0x80000000 of the memory space, and is 32MiB long. For ROM applications, all of the SDRAM is available for use. For JTAG applications the application is loaded from 0x80000000 with the remaining SDRAM after the code+data available for application use.

For RAM startup applications, SDRAM below 0x80008000 is reserved for the debug monitor (e.g. RedBoot).

External SRAM

This is located at address 0x64000000 of the memory space, and is 2MiB long. For SRAMEXT applications, all of the external SRAM is available for use.

Internal FLASH

This is located at address 0x08000000 of the memory space and will be mapped to 0x00000000 at reset. This region is 2048KiB in size. ROM and ROMINT applications are by default configured to run from this memory.

External FLASH

This is located at address 0x60000000 of the memory space. This region is 16MiB in size.

On-Chip Peripherals

These are accessible at locations 0x40000000 and 0xE0000000 upwards. Descriptions of the contents can be found in the STM32 User Manual.

Linker Scripts

The platform linker scripts define the following symbols:

hal_vsr_table

This defines the location of the VSR table. This is set to 0x20000000 for all startup types, and space for 98 entries is reserved.

hal_virtual_vector_table

This defines the location of the virtual vector table used to communicate between an ROM monitor and an eCos application. This is allocated right after the VSR table, at 0x200001AC.

hal_interrupt_stack

This defines the location of the interrupt stack. This is allocated to the top of internal SRAM, 0x20030000.

hal_startup_stack

This defines the location of the startup stack. For all startup types it is initially allocated at the half-way point of the interrupt stack.

I/O expander

If the CYGPKG_KERNEL is configured then a “helper” thread is created to handle forwarding of signals received by the I²C bus 1 based STMPE1600 I/O expander as eCos interrupts. The design approach minimises the overall system ISR latency which would occur if the I²C was directly accessed from the system ISR processing, at the cost of deferring the demultiplexing of the I/O expander interrupt source.

Device drivers and applications can access the signals using the same APIs as for standard STM32 GPIO lines, with respect to attaching interrupt handlers or examining/setting pin state.

Note: The priority of the ioexp_helper_thread() should be configured as high as possible, to minimise the latency in forwarding the de-multiplexed “virtual” interrupt sources to the relevant device driver (e.g. Ethernet PHY status change).

Diagnostic LEDs

Four LEDs are fitted on the board for diagnostic purposes and are labelled LD1 (green), LD2 (orange), LD3 (red) and LD4 (blue).

The platform HAL header file at <cyg/hal/plf_io.h> defines the following convenience function to allow the LEDs to be set:

extern void hal_stm324x9i_eval_led(char c);
    
The lowest 4-bits of the argument c correspond to each of the 4 LEDs (with LED0 as the least significant bit).

Table 262-1. LEDs

eCos LED GPIO manifest STM32F4 GPIO Bit number Board label Colour
CYGHWR_HAL_STM324X9I_EVAL_LED0 PG6 0 LD1 Green
CYGHWR_HAL_STM324X9I_EVAL_LED1 PG7 1 LD2 Orange
CYGHWR_HAL_STM324X9I_EVAL_LED2 PG10 2 LD3 Red
CYGHWR_HAL_STM324X9I_EVAL_LED3 PG12 3 LD4 Blue

The platform HAL will automatically light LED0 when the platform initialisation is complete, however the LEDs are then free for application use.

Note: If the CDL option CYGPKG_HAL_CORTEXM_STM32_STM324X9I_EVAL_SPI1_FLASH is configured (for example, as is the case for the modified “drb” platform with externally attached SPI flash) then the HAL_PLF_DEVS_DISK_MMC_FEEDBACK macro is defined by the platform plf_io.h to provide MMC/SD card access feedback using the CYGHWR_HAL_STM324X9I_EVAL_LED3 (blue) LED.

Flash wait states

The STM324X9I-EVAL platform HAL provides a configuration option to set the number of Flash read wait states to use: CYGNUM_HAL_CORTEXM_STM32_FLASH_WAIT_STATES. It is important to verify and if necessary update this value if changing the CPU clock (HCLK) frequency or CPU voltage. Consult the STM32 Flash programming manual (PM0081) for appropriate values for different clock speeds or voltages. The default of 5 reflects a supply voltage of 3.3V and HCLK of 168MHz.

Real-time characterization

The tm_basic kernel test gives statistics gathered about the real-time characterization and performance of the kernel. The sample output is shown here for information. The test was built for SRAM startup with optimization flag -O2, since it provides the best performance as both code and data could remain on-chip.

             Startup, main thrd : stack used   344 size  1536
             Startup : Idlethread stack used    84 size  1280

eCos Kernel Timings
Notes: all times are in microseconds (.000001) unless otherwise stated

Reading the hardware clock takes 0 'ticks' overhead
... this value will be factored out of all other measurements
Clock interrupt took    5.00 microseconds (5 raw clock ticks)

Testing parameters:
   Clock samples:            32
   Threads:                   8
   Thread switches:         128
   Mutexes:                  16
   Mailboxes:                16
   Semaphores:               16
   Scheduler operations:    128
   Counters:                 16
   Flags:                    16
   Alarms:                   16
   Stack Size:             1088


                                 Confidence
     Ave     Min     Max     Var  Ave  Min  Function
  ======  ======  ======  ====== ========== ========
INFO:<Ctrl-C disabled until test completion>
    4.00    4.00    4.00    0.00  100% 100% Create thread
    1.00    1.00    1.00    0.00  100% 100% Yield thread [all suspended]
    0.88    0.00    1.00    0.22   87%  12% Suspend [suspended] thread
    0.88    0.00    1.00    0.22   87%  12% Resume thread
    1.25    1.00    2.00    0.38   75%  75% Set priority
    0.38    0.00    1.00    0.47   62%  62% Get priority
    2.63    2.00    3.00    0.47   62%  37% Kill [suspended] thread
    1.00    1.00    1.00    0.00  100% 100% Yield [no other] thread
    1.38    1.00    2.00    0.47   62%  62% Resume [suspended low prio] thread
    0.88    0.00    1.00    0.22   87%  12% Resume [runnable low prio] thread
    1.13    1.00    2.00    0.22   87%  87% Suspend [runnable] thread
    0.88    0.00    1.00    0.22   87%  12% Yield [only low prio] thread
    0.88    0.00    1.00    0.22   87%  12% Suspend [runnable->not runnable]
    2.75    2.00    3.00    0.38   75%  25% Kill [runnable] thread
    2.25    2.00    3.00    0.38   75%  75% Destroy [dead] thread
    4.25    4.00    5.00    0.38   75%  75% Destroy [runnable] thread
    4.75    4.00    6.00    0.56   50%  37% Resume [high priority] thread
    1.54    1.00    2.00    0.50   53%  46% Thread switch

    0.20    0.00    1.00    0.31   80%  80% Scheduler lock
    0.79    0.00    1.00    0.33   78%  21% Scheduler unlock [0 threads]
    0.79    0.00    1.00    0.33   78%  21% Scheduler unlock [1 suspended]
    0.77    0.00    1.00    0.36   76%  23% Scheduler unlock [many suspended]
    0.80    0.00    1.00    0.32   79%  20% Scheduler unlock [many low prio]

    0.25    0.00    1.00    0.38   75%  75% Init mutex
    1.25    1.00    2.00    0.38   75%  75% Lock [unlocked] mutex
    1.19    1.00    2.00    0.30   81%  81% Unlock [locked] mutex
    1.00    1.00    1.00    0.00  100% 100% Trylock [unlocked] mutex
    0.88    0.00    1.00    0.22   87%  12% Trylock [locked] mutex
    0.31    0.00    1.00    0.43   68%  68% Destroy mutex
    5.00    5.00    5.00    0.00  100% 100% Unlock/Lock mutex

    0.44    0.00    1.00    0.49   56%  56% Create mbox
    0.13    0.00    1.00    0.22   87%  87% Peek [empty] mbox
    1.19    1.00    2.00    0.30   81%  81% Put [first] mbox
    0.31    0.00    1.00    0.43   68%  68% Peek [1 msg] mbox
    1.13    1.00    2.00    0.22   87%  87% Put [second] mbox
    0.06    0.00    1.00    0.12   93%  93% Peek [2 msgs] mbox
    1.19    1.00    2.00    0.30   81%  81% Get [first] mbox
    1.06    1.00    2.00    0.12   93%  93% Get [second] mbox
    1.00    1.00    1.00    0.00  100% 100% Tryput [first] mbox
    0.94    0.00    1.00    0.12   93%   6% Peek item [non-empty] mbox
    1.06    1.00    2.00    0.12   93%  93% Tryget [non-empty] mbox
    0.94    0.00    1.00    0.12   93%   6% Peek item [empty] mbox
    0.94    0.00    1.00    0.12   93%   6% Tryget [empty] mbox
    0.25    0.00    1.00    0.38   75%  75% Waiting to get mbox
    0.25    0.00    1.00    0.38   75%  75% Waiting to put mbox
    0.44    0.00    1.00    0.49   56%  56% Delete mbox
    3.50    3.00    4.00    0.50  100%  50% Put/Get mbox

    0.19    0.00    1.00    0.30   81%  81% Init semaphore
    0.81    0.00    1.00    0.31   81%  18% Post [0] semaphore
    0.94    0.00    1.00    0.12   93%   6% Wait [1] semaphore
    1.00    1.00    1.00    0.00  100% 100% Trywait [0] semaphore
    0.81    0.00    1.00    0.31   81%  18% Trywait [1] semaphore
    0.25    0.00    1.00    0.38   75%  75% Peek semaphore
    0.25    0.00    1.00    0.38   75%  75% Destroy semaphore
    3.00    3.00    3.00    0.00  100% 100% Post/Wait semaphore

    0.38    0.00    1.00    0.47   62%  62% Create counter
    0.38    0.00    1.00    0.47   62%  62% Get counter value
    0.19    0.00    1.00    0.30   81%  81% Set counter value
    1.19    1.00    2.00    0.30   81%  81% Tick counter
    0.25    0.00    1.00    0.38   75%  75% Delete counter

    0.25    0.00    1.00    0.38   75%  75% Init flag
    1.00    1.00    1.00    0.00  100% 100% Destroy flag
    1.00    1.00    1.00    0.00  100% 100% Mask bits in flag
    1.00    1.00    1.00    0.00  100% 100% Set bits in flag [no waiters]
    1.50    1.00    2.00    0.50  100%  50% Wait for flag [AND]
    1.31    1.00    2.00    0.43   68%  68% Wait for flag [OR]
    1.31    1.00    2.00    0.43   68%  68% Wait for flag [AND/CLR]
    1.38    1.00    2.00    0.47   62%  62% Wait for flag [OR/CLR]
    0.19    0.00    1.00    0.30   81%  81% Peek on flag

    0.69    0.00    1.00    0.43   68%  31% Create alarm
    1.44    1.00    2.00    0.49   56%  56% Initialize alarm
    1.00    1.00    1.00    0.00  100% 100% Disable alarm
    1.44    1.00    2.00    0.49   56%  56% Enable alarm
    0.94    0.00    1.00    0.12   93%   6% Delete alarm
    1.19    1.00    2.00    0.30   81%  81% Tick counter [1 alarm]
    3.81    3.00    4.00    0.31   81%  18% Tick counter [many alarms]
    2.00    2.00    2.00    0.00  100% 100% Tick & fire counter [1 alarm]
   17.88   17.00   18.00    0.22   87%  12% Tick & fire counters [>1 together]
    4.63    4.00    5.00    0.47   62%  37% Tick & fire counters [>1 separately]
    4.00    4.00    4.00    0.00  100% 100% Alarm latency [0 threads]
    4.00    4.00    4.00    0.00  100% 100% Alarm latency [2 threads]
    4.00    4.00    4.00    0.00  100% 100% Alarm latency [many threads]
    7.01    7.00    8.00    0.01   99%  99% Alarm -> thread resume latency

    0.00    0.00    0.00    0.00            Clock/interrupt latency

    2.71    2.00    3.00    0.00            Clock DSR latency

     204     204     204                    Worker thread stack used (stack size 1088)
            All done, main thrd : stack used   796 size  1536
            All done : Idlethread stack used   172 size  1280

Timing complete - 29330 ms total

PASS:<Basic timing OK>
EXIT:<done>
    
2017-02-09
Documentation license for this page: eCosPro License