The ARM architecture HAL provides support for members of the ARM7, ARM9, XScale and Cortex-A families. This includes support for the ARM, Thumb and Thumb2 instruction sets.
The architectural HAL provides support for those features which are common to all members of the ARM family, and for certain features which are present on some, but not all, members. This HAL contains support for CPU initialization, exception and interrupt entry and exit, thread context switching, interrupt masking, timer management, cache management and debugging. A typical eCos configuration will also contain a variant HAL package with support code for a family of processors, possibly a processor HAL package with support for one specific processor, and a platform HAL which contains the code needed for a specific hardware platform. For example the variant or processor HAL may define the exact interrupt controller hardware that is available, and the platform HAL will define the external interrupt vector connections.
If appropriate the variant or platform HAL may also enable support for an ARM architectural hardware Floating Point Unit (FPU). Not all ARM architectures provide hardware floating point as an option, and also not all of the various ARM architectural hardware floating point implementations are currently supported by this architectural HAL. For example, support is provided for the VFPv4-D16 co-processor available on some Cortex-A designs.
Support for SMP is available for the Cortex-A processor family based on the ARM MPCore cluster technology. This includes the Generic Interrupt Controller, Snoop Control Unit, private and global timers and the PL310 level 2 cache controller.