The powersaving system is initialized by calling
cyg_hal_sam9_powersave_init(). The argument
should be the IP address of this machine in network order. This can
usually be fetched from the bootp data for an interface after
completion of the call to
init_all_network_interfaces().
e.g. eth0_bootp_data.bp_ciaddr.s_addr.
A call to cyg_hal_sam9_powerdown() will put
the machine into a low power mode. This will involve switching to a
slower system clock speed, disabling all peripherals except those that
are defined to cause the system to wake up and return from this
function.
Configuration
The exact behaviour of the power saving system is controlled by the
following configuration options:
CYGPKG_HAL_ARM_ARM9_SAM9_POWERSAVE
This option controls the overall inclusion of the power saving
system.
Default value: on
CYGSEM_HAL_ARM_ARM9_SAM9_POWERSAVE_POLL_ETHERNET
This option enables polling of the ethernet interface for relevant ARP
packets and unicast IP packets. It is necessary for the CPU to run at
a higher CPU speed for this option to work.
Default value: off
CYGSEM_HAL_ARM_ARM9_SAM9_POWERSAVE_IDLE
If this option is set, the CPU will go into idle mode, which will
cause it to halt until an interrupt is delivered.
Default value: off
CYGVAR_HAL_ARM_ARM9_SAM9_POWERSAVE_ACTIVE_DEVICES
This option defines the devices that are to be kept running during
power down mode. An interrupt from one of these devices is usually the
only way of bringing the system out of idle mode. The value of this
option is a bit mask with bits set for each device that is to be kept
active. The bits correspond to the peripheral identifiers described in
the SAM9 documentation.
Default value: 0x00000000
CYGSEM_HAL_ARM_ARM9_SAM9_POWERSAVE_POLL_GPIO
This option control whether the power saving system will poll GPIO
pins during power saving. For this to work the CPU cannot be put into
idle mode.
Default value: on
CYGVAR_HAL_ARM_ARM9_SAM9_POWERSAVE_PIO_HI
This is an array of bitmasks of the bits in the PIO PDSR
registers. Within the array, index 0 corresponds to PIOA, index 1 to
PIOB and so on. For each set bit in these masks, if the value is seen
to be 1, then the low power mode will be terminated.
Default value: 0, 0, 0, 0
CYGVAR_HAL_ARM_ARM9_SAM9_POWERSAVE_PIO_LO
This is an array of bitmasks of the bits in the PIO PDSR
registers. Within the array, index 0 corresponds to PIOA, index 1 to
PIOB and so on. For each set bit in these masks, if the value is seen
to be 0, then the low power mode will be terminated.
Default value: 0, 0, 0, 0
CYGVAR_HAL_ARM_ARM9_SAM9_POWERSAVE_PIO_CHANGE
This is an array of bitmasks of the bits in the PIO PDSR
registers. Within the array, index 0 corresponds to PIOA, index 1 to
PIOB and so on. For each set bit in these masks, if the value is seen
to change between successive polls, then the low power mode will be
terminated.
Default value: 0, 0, 0, 0
CYGBLD_HAL_ARM_ARM9_SAM9_TEST_POWERSAVE
This option controls whether a simple test is built to exercise power
saving support. The test is not built by default as an external means
is required to wake the processor up by one of the above configured
mechanisms.
