The HAL Port

Name

HAL Port -- Implementation Details

Overview

This documentation explains how the eCos HAL specification has been mapped onto the board hardware, and should be read in conjunction with that specification. The platform HAL package complements the ARM architectural HAL, the ARM9 variant HAL and the i.MXxx processor HAL. It provides functionality which is specific to the target board.

Startup

Following a hard or soft reset, the HAL will initialize or reinitialize most of the on-chip peripherals. There is an exception for RAM startup applications which depend on a ROM monitor for certain services.

For ROM startup, the HAL will perform additional initialization. This is all done in the PLATFORM_SETUP1 macro in the assembler header file hal_platform_setup.h.

Linker Scripts and Memory Maps

The platform HAL package provides the memory layout information needed to generate the linker script. The key memory locations are as follows:

SDRAM

This is located at address 0x80000000 of the physical memory space and is 64MiB in size. The HAL configures the MMU to retain the SDRAM at virtual address 0x80000000, but in order to assign hardware exception vectors vectors at address 0x00000000, the HAL also uses the MMU to create an uncached clone of this memory at virtual address 0x00000000. The first 32 bytes are used for hardware exception vectors. The next 32 bytes are used for the VSR table and the next 256 bytes are normally used for the eCos virtual vectors, allowing RAM-based applications to use services provided by the ROM monitor. Memory is required for the MMU tables, and must be aligned on a 16Kbyte boundary. These therefore occupy memory from 0x4000 to 0x8000. 1MiB at 0x83f00000 is reserved for the LCD display frame buffer and is identity mapped uncached. For ROM startup, all remaining SDRAM is available. For RAM startup, available RAM starts at virtual location 0x80100000, with the bottom 1MB reserved for use by RedBoot. ROM applications are relocated starting at 0x80008000.

On-chip SRAM

There is 128KiB of SRAM which is identity mapped uncached at 0x78000000. eCos makes no current use of this memory, so it is available for application use.

SPI NOR Flash

SPI NOR flash media can only be accessed with the Flash API. For the purposes of this API a placeholder address range has been allocated as if the Flash is present at this address. The base of this address range is 0x70000000. This reserved range is not real memory and any attempt to access it directly by the processor other than via the Flash API will result in a memory address exception.

On-chip Peripheral Registers

These are located at various addresses in the physical memory space. When the MMU is enabled, it sets up a direct, uncached, unbuffered mapping so that these registers remain accessible at their physical locations.

Off-chip Peripherals

eCos uses the SDRAM, Ethernet PHY, and SPI flash and I2C power controllers on the board. eCos does not currently make any use of any other off-chip peripherals present on this board.

Real-time characterization

The tm_basic kernel test gives statistics gathered about the real-time characterization and performance of the kernel. The sample output is shown here for information. The test was built in ARM mode, which provides better performance than Thumb mode.

             Startup, main thrd : stack used   380 size  1792
             Startup :  Interrupt stack used  4096 size  4096
             Startup : Idlethread stack used    96 size  1280

eCos Kernel Timings
Notes: all times are in microseconds (.000001) unless otherwise stated

Reading the hardware clock takes 0 'ticks' overhead
... this value will be factored out of all other measurements
Clock interrupt took    3.09 microseconds (3 raw clock ticks)

Testing parameters:
   Clock samples:            32
   Threads:                  64
   Thread switches:         128
   Mutexes:                  32
   Mailboxes:                32
   Semaphores:               32
   Scheduler operations:    128
   Counters:                 32
   Flags:                    32
   Alarms:                   32
   Stack Size:             1088


                                 Confidence
     Ave     Min     Max     Var  Ave  Min  Function
  ======  ======  ======  ====== ========== ========
    4.05    3.00    8.00    0.42   65%  17% Create thread
    0.47    0.00    2.00    0.51   54%  54% Yield thread [all suspended]
    0.72    0.00    2.00    0.43   68%  29% Suspend [suspended] thread
    0.47    0.00    1.00    0.50   53%  53% Resume thread
    0.75    0.00    2.00    0.40   71%  26% Set priority
    0.23    0.00    1.00    0.36   76%  76% Get priority
    1.52    1.00    6.00    0.56   98%  54% Kill [suspended] thread
    0.47    0.00    1.00    0.50   53%  53% Yield [no other] thread
    0.83    0.00    2.00    0.34   76%  20% Resume [suspended low prio] thread
    0.53    0.00    2.00    0.51   50%  48% Resume [runnable low prio] thread
    0.58    0.00    1.00    0.49   57%  42% Suspend [runnable] thread
    0.47    0.00    2.00    0.51   54%  54% Yield [only low prio] thread
    0.45    0.00    1.00    0.50   54%  54% Suspend [runnable->not runnable]
    1.34    1.00    3.00    0.46   67%  67% Kill [runnable] thread
    1.22    1.00    4.00    0.36   81%  81% Destroy [dead] thread
    2.03    1.00    4.00    0.21   82%   7% Destroy [runnable] thread
    3.03    2.00    7.00    0.46   60%  20% Resume [high priority] thread
    0.75    0.00    4.00    0.41   71%  27% Thread switch

    0.16    0.00    1.00    0.26   84%  84% Scheduler lock
    0.39    0.00    1.00    0.48   60%  60% Scheduler unlock [0 threads]
    0.40    0.00    1.00    0.48   60%  60% Scheduler unlock [1 suspended]
    0.40    0.00    1.00    0.48   60%  60% Scheduler unlock [many suspended]
    0.39    0.00    1.00    0.48   60%  60% Scheduler unlock [many low prio]

    0.28    0.00    1.00    0.40   71%  71% Init mutex
    0.63    0.00    2.00    0.51   56%  40% Lock [unlocked] mutex
    0.69    0.00    4.00    0.56   56%  40% Unlock [locked] mutex
    0.50    0.00    1.00    0.50  100%  50% Trylock [unlocked] mutex
    0.41    0.00    1.00    0.48   59%  59% Trylock [locked] mutex
    0.22    0.00    1.00    0.34   78%  78% Destroy mutex
    2.94    2.00    6.00    0.29   81%  15% Unlock/Lock mutex

    0.47    0.00    1.00    0.50   53%  53% Create mbox
    0.47    0.00    1.00    0.50   53%  53% Peek [empty] mbox
    0.63    0.00    2.00    0.51   56%  40% Put [first] mbox
    0.13    0.00    1.00    0.22   87%  87% Peek [1 msg] mbox
    0.53    0.00    2.00    0.53   96%  50% Put [second] mbox
    0.19    0.00    1.00    0.30   81%  81% Peek [2 msgs] mbox
    0.63    0.00    2.00    0.51   56%  40% Get [first] mbox
    0.66    0.00    1.00    0.45   65%  34% Get [second] mbox
    0.50    0.00    2.00    0.53   96%  53% Tryput [first] mbox
    0.47    0.00    1.00    0.50   53%  53% Peek item [non-empty] mbox
    0.53    0.00    2.00    0.53   96%  50% Tryget [non-empty] mbox
    0.50    0.00    1.00    0.50  100%  50% Peek item [empty] mbox
    0.47    0.00    1.00    0.50   53%  53% Tryget [empty] mbox
    0.19    0.00    1.00    0.30   81%  81% Waiting to get mbox
    0.16    0.00    1.00    0.26   84%  84% Waiting to put mbox
    0.25    0.00    1.00    0.38   75%  75% Delete mbox
    1.19    1.00    5.00    0.34   90%  90% Put/Get mbox

    0.19    0.00    1.00    0.30   81%  81% Init semaphore
    0.47    0.00    1.00    0.50   53%  53% Post [0] semaphore
    0.47    0.00    1.00    0.50   53%  53% Wait [1] semaphore
    0.47    0.00    2.00    0.53   56%  56% Trywait [0] semaphore
    0.47    0.00    1.00    0.50   53%  53% Trywait [1] semaphore
    0.19    0.00    1.00    0.30   81%  81% Peek semaphore
    0.16    0.00    1.00    0.26   84%  84% Destroy semaphore
    1.06    1.00    3.00    0.12   96%  96% Post/Wait semaphore

    0.53    0.00    1.00    0.50   53%  46% Create counter
    0.44    0.00    1.00    0.49   56%  56% Get counter value
    0.25    0.00    1.00    0.38   75%  75% Set counter value
    0.56    0.00    1.00    0.49   56%  43% Tick counter
    0.22    0.00    1.00    0.34   78%  78% Delete counter

    0.22    0.00    1.00    0.34   78%  78% Init flag
    0.56    0.00    3.00    0.56   96%  50% Destroy flag
    0.44    0.00    1.00    0.49   56%  56% Mask bits in flag
    0.50    0.00    2.00    0.53   96%  53% Set bits in flag [no waiters]
    0.59    0.00    3.00    0.56   50%  46% Wait for flag [AND]
    0.63    0.00    1.00    0.47   62%  37% Wait for flag [OR]
    0.53    0.00    1.00    0.50   53%  46% Wait for flag [AND/CLR]
    0.56    0.00    1.00    0.49   56%  43% Wait for flag [OR/CLR]
    0.09    0.00    1.00    0.17   90%  90% Peek on flag

    0.66    0.00    2.00    0.49   59%  37% Create alarm
    0.88    0.00    3.00    0.33   78%  18% Initialize alarm
    0.50    0.00    2.00    0.53   96%  53% Disable alarm
    0.72    0.00    2.00    0.45   65%  31% Enable alarm
    0.50    0.00    1.00    0.50  100%  50% Delete alarm
    0.56    0.00    1.00    0.49   56%  43% Tick counter [1 alarm]
    2.25    2.00    3.00    0.38   75%  75% Tick counter [many alarms]
    0.88    0.00    2.00    0.27   81%  15% Tick & fire counter [1 alarm]
   11.78   11.00   12.00    0.34   78%  21% Tick & fire counters [>1 together]
    2.53    2.00    3.00    0.50   53%  46% Tick & fire counters [>1 separately]
    2.03    2.00    3.00    0.06   96%  96% Alarm latency [0 threads]
    2.74    2.00    3.00    0.38   74%  25% Alarm latency [2 threads]
    6.89    6.00    9.00    0.47   59%  26% Alarm latency [many threads]
    4.05    4.00    9.00    0.11   98%  98% Alarm -> thread resume latency

    1.30    1.00    4.00    0.00            Clock/interrupt latency

    1.24    1.00    5.00    0.00            Clock DSR latency

     242     172     272                    Worker thread stack used (stack size 1088)
            All done, main thrd : stack used   956 size  1792
            All done :  Interrupt stack used   156 size  4096
            All done : Idlethread stack used   408 size  1280

Timing complete - 29810 ms total

PASS:<Basic timing OK>
EXIT:<done>
   

Other Issues

The platform HAL does not affect the implementation of other parts of the eCos HAL specification. The i.MXxx processor HAL, ARM9 variant HAL, and the ARM architectural HAL documentation should be consulted for further details.

Bonjour Conformance Test

This section just provides information regarding the specific MCIMX25WPDK platform Bonjour test. For more detail regarding Bonjour testing please reference the Bonjour Conformance Test section of the mDNS package documentation.

For the mDNS Responder package testing the following equipment was used.

  • Unit-Under-Test (UUT)

    The mcimx25wpdk target platform being tested, executing a suitable eCosPro mDNS configuration.

  • Mac Mini (OS: 10.9.3)

    Executing the BonjourConformanceTest v1.3.0 in a Terminal shell window, and the Safari v7.0.4 web-browser.

  • Billion BiPAC 7800N

    10base-T (wired) Ethernet connections to the UUT and the Mac Mini.

The result for an actual BCT run using the mdns_example application, executing on the MCIMX25WPDK platform, is available in the doc/bct_mcimx25wpdk_result.txt file. This file is the original, as produced by the BCT application. For reference, the doc/bct_mcimx25wpdk_terminal.txt contains the execution output captured from the MacOS Terminal window. Both of these files can be found in the mcimx25x HAL documentation directory: packages/hal/arm/arm9/mcimx25x/<version>/doc

The following is a listing of the doc/bct_mcimx25wpdk_result.txt file.

Bonjour Conformance Test Version 1.3.0
Started   Mon Jun  9 09:57:26 2014
Completed Mon Jun  9 13:19:23 2014


Link-Local Address Allocation
-----------------------------
	PASSED: INITIAL PROBING
	PASSED: PROBING: RATE LIMITING
	PASSED: PROBING: CONFLICTING SIMULTANEOUS PROBES
	PASSED: PROBING: PROBE DENIALS
	PASSED: PROBING COMPLETION
	WARNING: SUBSEQUENT CONFLICTS: RE-PROBE AFTER FIRST CONFLICT
	WARNING: SUBSEQUENT CONFLICTS: RE-PROBE AFTER FIRST CONFLICT
	WARNING: SUBSEQUENT CONFLICTS: RE-PROBE AFTER FIRST CONFLICT
	WARNING: SUBSEQUENT CONFLICTS: RE-PROBE AFTER FIRST CONFLICT
	WARNING: SUBSEQUENT CONFLICTS: RE-PROBE AFTER FIRST CONFLICT
	WARNING: SUBSEQUENT CONFLICTS: RE-PROBE AFTER FIRST CONFLICT
	WARNING: SUBSEQUENT CONFLICTS: RE-PROBE AFTER FIRST CONFLICT
	WARNING: SUBSEQUENT CONFLICTS: RE-PROBE AFTER FIRST CONFLICT
	WARNING: SUBSEQUENT CONFLICTS: RE-PROBE AFTER FIRST CONFLICT

	PASSED: SUBSEQUENT CONFLICTS
	PASSED: HOT-PLUG: USE OF PREVIOUS ADDRESS AS FIRST PROBE CANDIDATE
	PASSED: CABLE CHANGE HANDLING
	PASSED: PREMATURE MDNS PROBING
PASSED with 9 warning(s).

Multicast DNS
-----------------------------
	PASSED: INITIAL PROBING
	PASSED: PROBING: SIMULTANEOUS PROBE CONFLICT
	PASSED: PROBING: RATE LIMITING
	PASSED: PROBING: PROBE DENIALS
	PASSED: WINNING SIMULTANEOUS PROBES - ANNOUNCEMENTS
	PASSED: WINNING SIMULTANEOUS PROBES: WINNING SIMULTANEOUS PROBES
	PASSED: SRV PROBING/ANNOUNCEMENTS
	PASSED: SUBSEQUENT CONFLICT - ANNOUNCEMENTS
	PASSED: SUBSEQUENT CONFLICT - A
	PASSED: SUBSEQUENT CONFLICT - ANNOUNCEMENTS
	PASSED: SUBSEQUENT CONFLICT - SRV
	PASSED: SIMPLE REPLY VERIFICATION
	PASSED: SHARED REPLY TIMING - UNIFORM RANDOM REPLY TIME DISTRIBUTION
	PASSED: SHARED REPLY TIMING
	PASSED: MULTIPLE QUESTIONS - SHARED REPLY TIMING - UNIFORM RANDOM REPLY TIME DISTRIBUTION
	PASSED: MULTIPLE QUESTIONS - SHARED REPLY TIMING
	PASSED: REPLY AGGREGATION
	PASSED: MANUAL NAME CHANGE - ANNOUNCEMENTS
	PASSED: HOT-PLUGGING: INITIAL PROBING
	PASSED: HOT-PLUGGING: PROBING: SIMULTANEOUS PROBE CONFLICT
	PASSED: HOT-PLUGGING: PROBING: RATE LIMITING
	PASSED: HOT-PLUGGING: PROBING: PROBE DENIALS
	PASSED: HOT-PLUGGING: WINNING SIMULTANEOUS PROBES - ANNOUNCEMENTS
	PASSED: HOT-PLUGGING: WINNING SIMULTANEOUS PROBES: WINNING SIMULTANEOUS PROBES
	PASSED: HOT-PLUGGING: SRV PROBING/ANNOUNCEMENTS
	PASSED: HOT-PLUGGING: SUBSEQUENT CONFLICT - ANNOUNCEMENTS
	PASSED: HOT-PLUGGING: SUBSEQUENT CONFLICT - A
	PASSED: HOT-PLUGGING: SUBSEQUENT CONFLICT - ANNOUNCEMENTS
	PASSED: HOT-PLUGGING: SUBSEQUENT CONFLICT - SRV
	PASSED: HOT-PLUGGING
	PASSED: NO DUPLICATE RECORDS IN PACKETS
	PASSED: REQUIRED ADDITIONAL RECORDS IN ANSWERS
	PASSED: LEGAL CHARACTERS IN ADDRESS RECORD NAMES
	PASSED: CACHE FLUSH BIT SET IN NON-SHARED RESPONSES
	PASSED: CACHE FLUSH BIT NOT SET IN PROPOSED ANSWER OF PROBES
PASSED with 0 warning(s).

Mixed-Network Interoperability
-----------------------------
	PASSED: LINK-LOCAL TO ROUTABLE COMMUNICATION
	PASSED: ROUTABLE TO LINK-LOCAL COMMUNICATION
	PASSED: CACHE FLUSH BIT NOT SET IN UNICAST RESPONSE
	PASSED: UNICAST INTEROPERABILITY
	PASSED: CHATTINESS
	PASSED: mDNS IP TTL CHECK
	PASSED: DUPLICATE RECORDS CHECK
	PASSED: ADDITIONAL RECORDS IN ANSWER CHECK
PASSED with 0 warning(s).


******************************************************************************
	CONGRATULATIONS: You successfully passed the Bonjour Conformance test
******************************************************************************
    

2017-02-09
Documentation license for this page: eCosPro License