This documentation explains how the eCos HAL specification has been
mapped onto the IQ80321 hardware, and should be read in conjunction
with that specification. The IQ80321 platform HAL package complements
the ARM architectural HAL, the XScale core HAL and the IOP321 (VERDE)
variant HAL. It provides functionality which is specific to the target
board.
Startup
Following a hard or soft reset the HAL will initialize or reinitialize
the on-chip peripherals that are used by eCos. There is an exception
for RAM startup applications which depend on a ROM monitor for certain
services.
For ROM startup, the HAL will perform additional
initialization, setting up the external SDRAM and programming the
various internal registers. This is all done in the
PLATFORM_SETUP1 macro in the assembler
header file hal_platform_setup.h.
Memory Maps
The RAM based page table is located at RAM start + 0x4000.
NOTE: The virtual memory map in this section uses a C, B, and X column to indicate
the caching policy for the region.
X C B Description
- - - ---------------------------------------------
0 0 0 Uncached/Unbuffered
0 0 1 Uncached/Buffered
0 1 0 Cached/Buffered Write Through, Read Allocate
0 1 1 Cached/Buffered Write Back, Read Allocate
1 0 0 Invalid -- not used
1 0 1 Uncached/Buffered No write buffer coalescing
1 1 0 Mini DCache - Policy set by Aux Ctl Register
1 1 1 Cached/Buffered Write Back, Read/Write Allocate
Physical Address Range Description
----------------------- ----------------------------------
0x00000000 - 0x7fffffff ATU Outbound Direct Window
0x80000000 - 0x900fffff ATU Outbound Translate Windows
0xa0000000 - 0xbfffffff SDRAM
0xf0000000 - 0xf0800000 FLASH (PBIU CS0)
0xfe800000 - 0xfe800fff UART (PBIU CS1)
0xfe840000 - 0xfe840fff Left 7-segment LED (PBIU CS3)
0xfe850000 - 0xfe850fff Right 7-segment LED (PBIU CS2)
0xfe8d0000 - 0xfe8d0fff Rotary Switch (PBIU CS4)
0xfe8f0000 - 0xfe8f0fff Battery Status (PBIU CS5)
0xfff00000 - 0xffffffff Verde Memory mapped Registers
Default Virtual Map X C B Description
----------------------- - - - ----------------------------------
0x00000000 - 0x1fffffff 1 1 1 SDRAM
0x20000000 - 0x9fffffff 0 0 0 ATU Outbound Direct Window
0xa0000000 - 0xb00fffff 0 0 0 ATU Outbound Translate Windows
0xc0000000 - 0xdfffffff 0 0 0 Uncached alias for SDRAM
0xe0000000 - 0xe00fffff 1 1 1 Cache flush region (no phys mem)
0xf0000000 - 0xf0800000 0 1 0 FLASH (PBIU CS0)
0xfe800000 - 0xfe800fff 0 0 0 UART (PBIU CS1)
0xfe840000 - 0xfe840fff 0 0 0 Left 7-segment LED (PBIU CS3)
0xfe850000 - 0xfe850fff 0 0 0 Right 7-segment LED (PBIU CS2)
0xfe8d0000 - 0xfe8d0fff 0 0 0 Rotary Switch (PBIU CS4)
0xfe8f0000 - 0xfe8f0fff 0 0 0 Battery Status (PBIU CS5)
0xfff00000 - 0xffffffff 0 0 0 Verde Memory mapped Registers
Other Issues
The IQ80321 platform HAL does not affect the implementation of other
parts of the eCos HAL specification. The XScale core HAL, the IOP321
(VERDE) variant HAL, and the ARM architectural HAL documentation
should be consulted for further details.
