The HAL Port

Name

HAL Port -- Implementation Details

Overview

This documentation explains how the eCos HAL specification has been mapped onto the AT91SAM7A2-EK hardware, and should be read in conjunction with that specification. The AT91SAM7A2-EK platform HAL package complements the ARM architectural HAL, the AT91 variant HAL and the AT91SAM7 processor HAL. It provides functionality which is specific to the target board.

Startup

Following a hard or soft reset, the HAL will initialize or reinitialize most of the on-chip peripherals. There is an exception for RAM startup applications which depend on a ROM monitor or JTAG device for certain services.

For ROM startup, the HAL will perform additional initialization, setting up the PLL and programming the various internal registers. This is all done in the PLATFORM_SETUP1 macro in the assembler header file hal_platform_setup.h.

Linker Scripts and Memory Maps

The AT91SAM7 processor HAL package provides the memory layout information needed to generate the linker script. The key memory locations are as follows:

Flash

This is located at address 0x40000000 of the physical memory space.

RAM

This is located at address 0x48000000 of the physical memory space. During booting this memory is only available at this address, but during the boot process it is also remapped to location 0x00000000 in order to allow the hardware exception vectors to be in RAM. The first 32 bytes are used for hardware exception vectors. The next 32 bytes are used for the VSR table and the next 256 bytes are normally used for the eCos virtual vectors, allowing RAM-based applications to use services provided by the ROM monitor. For ROM startup, all remaining RAM is available. For RAM startup, available RAM starts at location 0x48008000, with the bottom 32KiB reserved for use by RedBoot.

On-chip Peripheral Registers

These are located at address 0xFF000000 in the physical memory space.

Real-time characterization

The tm_basic kernel test gives statistics gathered about the real-time characterization and performance of the kernel. The sample output is shown here for information. The test was built in ARM mode, which provided better performance than Thumb mode.

            Startup, main stack : stack used   416 size  3920
             Startup :  Interrupt stack used   148 size  4096
             Startup : Idlethread stack used    88 size  2048

eCos Kernel Timings
Notes: all times are in microseconds (.000001) unless otherwise stated

Reading the hardware clock takes 1 'ticks' overhead
... this value will be factored out of all other measurements
Clock interrupt took   61.00 microseconds (57 raw clock ticks)

Testing parameters:
   Clock samples:            32
   Threads:                  10
   Thread switches:         128
   Mutexes:                  32
   Mailboxes:                32
   Semaphores:               32
   Scheduler operations:    128
   Counters:                 32
   Flags:                    32
   Alarms:                   32


                                 Confidence
     Ave     Min     Max     Var  Ave  Min  Function
  ======  ======  ======  ====== ========== ========
   46.93   43.73   50.13    1.71   40%  30% Create thread
    8.96    8.53    9.60    0.51   60%  60% Yield thread [all suspended]
    9.28    8.53    9.60    0.45   70%  30% Suspend [suspended] thread
   10.03    9.60   10.67    0.51   60%  60% Resume thread
   13.87   13.87   13.87    0.00  100% 100% Set priority
    1.49    1.07    2.13    0.51   60%  60% Get priority
   32.00   32.00   32.00    0.00  100% 100% Kill [suspended] thread
    9.07    8.53    9.60    0.53  100%  50% Yield [no other] thread
   16.96   16.00   17.07    0.19   90%  10% Resume [suspended low prio] thread
    9.60    9.60    9.60    0.00  100% 100% Resume [runnable low prio] thread
   12.80   12.80   12.80    0.00  100% 100% Suspend [runnable] thread
    8.96    8.53    9.60    0.51   60%  60% Yield [only low prio] thread
    9.17    8.53    9.60    0.51   60%  40% Suspend [runnable->not runnable]
   32.00   32.00   32.00    0.00  100% 100% Kill [runnable] thread
   23.15   22.40   23.47    0.45   70%  30% Destroy [dead] thread
   46.51   45.87   46.93    0.51   60%  40% Destroy [runnable] thread
   62.29   60.80   69.33    1.41   60%  90% Resume [high priority] thread
   24.07   23.47   32.00    0.59   50%  49% Thread switch

    1.60    1.07    2.13    0.53  100%  50% Scheduler lock
    6.93    6.40    7.47    0.53  100%  50% Scheduler unlock [0 threads]
    6.93    6.40    7.47    0.53  100%  50% Scheduler unlock [1 suspended]
    6.93    6.40    7.47    0.53  100%  50% Scheduler unlock [many suspended]
    6.93    6.40    7.47    0.53  100%  50% Scheduler unlock [many low prio]

    2.67    2.13    3.20    0.53  100%  50% Init mutex
   10.40    9.60   10.67    0.40   75%  25% Lock [unlocked] mutex
   11.73   11.73   11.73    0.00  100% 100% Unlock [locked] mutex
    9.87    9.60   10.67    0.40   75%  75% Trylock [unlocked] mutex
    8.47    7.47    8.53    0.12   93%   6% Trylock [locked] mutex
    1.07    1.07    1.07    0.00  100% 100% Destroy mutex
   62.57   61.87   62.93    0.48   65%  34% Unlock/Lock mutex

    3.53    3.20    4.27    0.46   68%  68% Create mbox
    1.00    0.00    1.07    0.12   93%   6% Peek [empty] mbox
   11.73   11.73   11.73    0.00  100% 100% Put [first] mbox
    1.00    0.00    1.07    0.12   93%   6% Peek [1 msg] mbox
   11.20   10.67   11.73    0.53  100%  50% Put [second] mbox
    1.00    0.00    1.07    0.12   93%   6% Peek [2 msgs] mbox
   11.67   10.67   11.73    0.12   93%   6% Get [first] mbox
   11.60   10.67   11.73    0.23   87%  12% Get [second] mbox
    9.53    8.53    9.60    0.12   93%   6% Tryput [first] mbox
    8.93    8.53    9.60    0.50   62%  62% Peek item [non-empty] mbox
   10.40    9.60   10.67    0.40   75%  25% Tryget [non-empty] mbox
    8.73    8.53    9.60    0.32   81%  81% Peek item [empty] mbox
    9.13    8.53    9.60    0.52   56%  43% Tryget [empty] mbox
    1.13    1.07    2.13    0.12   93%  93% Waiting to get mbox
    1.13    1.07    2.13    0.12   93%  93% Waiting to put mbox
    3.47    3.20    4.27    0.40   75%  75% Delete mbox
   43.40   42.67   43.73    0.46   68%  31% Put/Get mbox

    2.27    2.13    3.20    0.23   87%  87% Init semaphore
    8.60    8.53    9.60    0.12   93%  93% Post [0] semaphore
    9.60    9.60    9.60    0.00  100% 100% Wait [1] semaphore
    8.00    7.47    8.53    0.53  100%  50% Trywait [0] semaphore
    8.33    7.47    8.53    0.33   81%  18% Trywait [1] semaphore
    2.47    2.13    3.20    0.46   68%  68% Peek semaphore
    1.20    1.07    2.13    0.23   87%  87% Destroy semaphore
   39.17   38.40   39.47    0.43   71%  28% Post/Wait semaphore

    3.73    3.20    4.27    0.53  100%  50% Create counter
    1.33    1.07    2.13    0.40   75%  75% Get counter value
    1.33    1.07    2.13    0.40   75%  75% Set counter value
   10.20    9.60   10.67    0.52   56%  43% Tick counter
    1.27    1.07    2.13    0.32   81%  81% Delete counter

    2.27    2.13    3.20    0.23   87%  87% Init flag
    9.13    8.53    9.60    0.52   56%  43% Destroy flag
    7.93    7.47    8.53    0.52   56%  56% Mask bits in flag
    9.53    8.53    9.60    0.12   93%   6% Set bits in flag [no waiters]
   13.87   13.87   13.87    0.00  100% 100% Wait for flag [AND]
   13.60   12.80   13.87    0.40   75%  25% Wait for flag [OR]
   13.93   13.87   14.93    0.12   93%  93% Wait for flag [AND/CLR]
   13.73   12.80   13.87    0.23   87%  12% Wait for flag [OR/CLR]
    0.93    0.00    1.07    0.23   87%  12% Peek on flag

    5.97    5.33    6.40    0.51   59%  40% Create alarm
   17.60   17.07   18.13    0.53  100%  50% Initialize alarm
    8.23    7.47    8.53    0.43   71%  28% Disable alarm
   16.23   16.00   17.07    0.36   78%  78% Enable alarm
    9.87    9.60   10.67    0.40   75%  75% Delete alarm
   11.87   11.73   12.80    0.23   87%  87% Tick counter [1 alarm]
   74.13   73.60   74.67    0.53  100%  50% Tick counter [many alarms]
   22.67   22.40   23.47    0.40   75%  75% Tick & fire counter [1 alarm]
  452.10  450.13  504.53    3.28   96%  96% Tick & fire counters [>1 together]
   85.70   85.33   86.40    0.48   65%  65% Tick & fire counters [>1 separately]
   58.67   58.67   58.67    0.00  100% 100% Alarm latency [0 threads]
   65.02   58.67   72.53    3.94   42%  30% Alarm latency [2 threads]
   64.89   58.67   72.53    3.99   42%  35% Alarm latency [many threads]
  100.33  100.27  108.80    0.13   99%  99% Alarm -> thread resume latency

   10.68   10.67   11.73    0.00            Clock/interrupt latency

   24.98   21.33  146.13    0.00            Clock DSR latency

  274    232     292  (main stack:   804)  Thread stack used (1360 total)
           All done, main stack : stack used   804 size  3920
            All done :  Interrupt stack used   208 size  4096
            All done : Idlethread stack used   252 size  2048

Timing complete - 30940 ms total

PASS:<Basic timing OK>
EXIT:<done>
    

Other Issues

The AT91SAM7A2-EK platform HAL does not affect the implementation of other parts of the eCos HAL specification. The AT91SAM7 processor HAL, AT91 variant HAL, and the ARM architectural HAL documentation should be consulted for further details.

2017-02-09
Documentation license for this page: eCosPro License