This driver supports the ADC devices available in some variants of the
ST STR7XX family of microprocessors.
Sample Size
The STR7XX ADC produces 12 bit samples. Therefore this driver sets
CYGNUM_IO_ADC_SAMPLE_SIZE to 12. This will cause
the generic layer to define cyg_adc_sample_t as a 16 bit
value.
Sample Rates
The ADC hardware is limited to a maximum of 1K samples per
channel. Since channels are sampled on a round-robin basis at 4 times
this rate, this means that the total sample rate is 4K samples per
second.
The option CYGNUM_DEVS_ADC_ARM_STR7XX_DEFAULT_RATE
defines a default sample rate and is initially set to 500.
Configuration
For each channel X supported the CDL script
provides the following configuration options: