G.4.5 PowerPC Features

The org.gnu.gdb.power.core feature is required for PowerPC targets. It should contain registers r0 through r31, pc, msr, cr, lr, ctr, and xer. They may be 32-bit or 64-bit depending on the target.

The org.gnu.gdb.power.fpu feature is optional. It should contain registers f0 through f31 and fpscr.

The org.gnu.gdb.power.altivec feature is optional. It should contain registers vr0 through vr31, vscr, and vrsave.

The org.gnu.gdb.power.vsx feature is optional. It should contain registers vs0h through vs31h. gdb will combine these registers with the floating point registers (f0 through f31) and the altivec registers (vr0 through vr31) to present the 128-bit wide registers vs0 through vs63, the set of vector registers for POWER7.

The org.gnu.gdb.power.spe feature is optional. It should contain registers ev0h through ev31h, acc, and spefscr. SPE targets should provide 32-bit registers in org.gnu.gdb.power.core and provide the upper halves in ev0h through ev31h. gdb will combine these to present registers ev0 through ev31 to the user.