Next: , Previous: s390 Register, Up: s390 Syntax Instruction Mnemonics

All instructions documented in the Principles of Operation are supported with the mnemonic and order of operands as described. The instruction mnemonic identifies the instruction format (s390 Formats) and the specific operation code for the instruction. For example, the lr mnemonic denotes the instruction format RR with the operation code 0x18.

The definition of the various mnemonics follows a scheme, where the first character usually hint at the type of the instruction:


a add instruction, for example al for add logical 32-bit
b branch instruction, for example bc for branch on condition
c compare or convert instruction, for example cr for compare register 32-bit
d divide instruction, for example dlr devide logical register 64-bit to 32-bit
i insert instruction, for example ic insert character
l load instruction, for example ltr load and test register
mv move instruction, for example mvc move character
m multiply instruction, for example mh multiply halfword
n and instruction, for example ni and immediate
o or instruction, for example oc or character
sla, sll shift left single instruction
sra, srl shift right single instruction
st store instruction, for example stm store multiple
s subtract instruction, for example slr subtract logical 32-bit
t test or translate instruction, of example tm test under mask
x exclusive or instruction, for example xc exclusive or character

Certain characters at the end of the mnemonic may describe a property of the instruction:


c the instruction uses a 8-bit character operand
f the instruction extends a 32-bit operand to 64 bit
g the operands are treated as 64-bit values
h the operand uses a 16-bit halfword operand
i the instruction uses an immediate operand
l the instruction uses unsigned, logical operands
m the instruction uses a mask or operates on multiple values
r if r is the last character, the instruction operates on registers
y the instruction uses 20-bit displacements

There are many exceptions to the scheme outlined in the above lists, in particular for the priviledged instructions. For non-priviledged instruction it works quite well, for example the instruction clgfr c: compare instruction, l: unsigned operands, g: 64-bit operands, f: 32- to 64-bit extension, r: register operands. The instruction compares an 64-bit value in a register with the zero extended 32-bit value from a second register. For a complete list of all mnemonics see appendix B in the Principles of Operation.