9.24 MIPS Dependent Features
as for mips architectures supports several
different mips processors, and MIPS ISA levels I through V, MIPS32,
and MIPS64. For information about the mips instruction set, see
MIPS RISC Architecture, by Kane and Heindrich (Prentice-Hall).
For an overview of mips assembly conventions, see “Appendix D:
Assembly Language Programming” in the same work.