9.24.1 Assembler options
- This option sets the largest size of an object that can be referenced
implicitly with the
gpregister. It is only accepted for targets that use ecoff format. The default value is 8.
- Any mips configuration of
ascan select big-endian or little-endian output at run time (unlike the other gnu development tools, which must be configured for one or the other). Use -EB to select big-endian output, and -EL for little-endian.
- Generate SVR4-style PIC. This option tells the assembler to generate
SVR4-style position-independent macro expansions. It also tells the
assembler to mark the output file as PIC.
- Generate VxWorks PIC. This option tells the assembler to generate VxWorks-style position-independent macro expansions.
- Generate code for a particular MIPS Instruction Set Architecture level.
-mips1 corresponds to the r2000 and r3000 processors,
-mips2 to the r6000 processor, -mips3 to the
r4000 processor, and -mips4 to the r8000 and
r10000 processors. -mips5, -mips32, -mips32r2,
-mips64, and -mips64r2
correspond to generic
MIPS V, MIPS32, MIPS32 Release 2, MIPS64,
and MIPS64 Release 2
ISA processors, respectively. You can also switch
instruction sets during the assembly; see Directives to override the ISA level.
- Some macros have different expansions for 32-bit and 64-bit registers.
The register sizes are normally inferred from the ISA and ABI, but these
flags force a certain group of registers to be treated as 32 bits wide at
all times. -mgp32 controls the size of general-purpose registers
and -mfp32 controls the size of floating-point registers.
.set fp=32directives allow the size of registers to be changed for parts of an object. The default value is restored by
On some MIPS variants there is a 32-bit mode flag; when this flag is set, 64-bit instructions generate a trap. Also, some 32-bit OSes only save the 32-bit registers on a context switch, so it is essential never to use the 64-bit registers.
- Assume that 64-bit registers are available. This is provided in the
interests of symmetry with -mgp32 and -mfp32.
.set fp=64directives allow the size of registers to be changed for parts of an object. The default value is restored by
- Generate code for the MIPS 16 processor. This is equivalent to putting
.set mips16at the start of the assembly file. -no-mips16 turns off this option.
- Enables the SmartMIPS extensions to the MIPS32 instruction set, which
provides a number of new instructions which target smartcard and
cryptographic applications. This is equivalent to putting
.set smartmipsat the start of the assembly file. -mno-smartmips turns off this option.
- Generate code for the MIPS-3D Application Specific Extension.
This tells the assembler to accept MIPS-3D instructions.
-no-mips3d turns off this option.
- Generate code for the MDMX Application Specific Extension.
This tells the assembler to accept MDMX instructions.
-no-mdmx turns off this option.
- Generate code for the DSP Release 1 Application Specific Extension.
This tells the assembler to accept DSP Release 1 instructions.
-mno-dsp turns off this option.
- Generate code for the DSP Release 2 Application Specific Extension.
This option implies -mdsp.
This tells the assembler to accept DSP Release 2 instructions.
-mno-dspr2 turns off this option.
- Generate code for the MT Application Specific Extension.
This tells the assembler to accept MT instructions.
-mno-mt turns off this option.
- Cause nops to be inserted if the read of the destination register
of an mfhi or mflo instruction occurs in the following two instructions.
- Insert nops to work around certain VR4120 errata. This option is
intended to be used on GCC-generated code: it is not designed to catch
all problems in hand-written assembler code.
- Insert nops to work around the VR4130 mflo/mfhi errata.
- Insert nops to work around the 24K eret/deret errata.
- Generate code for the LSI r4010 chip. This tells the assembler to
accept the r4010 specific instructions (addciu, ffc,
etc.), and to not schedule nop instructions around accesses to
the HI and LO registers. -no-m4010 turns off this
- Generate code for the MIPS r4650 chip. This tells the assembler to accept the mad and madu instruction, and to not schedule nop instructions around accesses to the HI and LO registers. -no-m4650 turns off this option.
- For each option -mnnnn, generate code for the MIPS
rnnnn chip. This tells the assembler to accept instructions
specific to that chip, and to schedule for that chip's hazards.
- Generate code for a particular MIPS cpu. It is exactly equivalent to
-mcpu, except that there are more value of cpu
understood. Valid cpu value are:
2000, 3000, 3900, 4000, 4010, 4100, 4111, vr4120, vr4130, vr4181, 4300, 4400, 4600, 4650, 5000, rm5200, rm5230, rm5231, rm5261, rm5721, vr5400, vr5500, 6000, rm7000, 8000, rm9000, 10000, 12000, 14000, 16000, 4kc, 4km, 4kp, 4ksc, 4kec, 4kem, 4kep, 4ksd, m4k, m4kp, 24kc, 24kf2_1, 24kf, 24kf1_1, 24kec, 24kef2_1, 24kef, 24kef1_1, 34kc, 34kf2_1, 34kf, 34kf1_1, 74kc, 74kf2_1, 74kf, 74kf1_1, 74kf3_2, 1004kc, 1004kf2_1, 1004kf, 1004kf1_1, 5kc, 5kf, 20kc, 25kf, sb1, sb1a, loongson2e, loongson2f, octeon, xlr
For compatibility reasons, nx and bfx are accepted as synonyms for nf1_1. These values are deprecated.
- Schedule and tune for a particular MIPS cpu. Valid cpu values are
identical to -march=cpu.
- Record which ABI the source code uses. The recognized arguments
are: 32, n32, o64, 64 and eabi.
- Equivalent to adding
.set nosym32to the beginning of the assembler input. See MIPS symbol sizes.
- This option is ignored. It is accepted for command-line compatibility with
other assemblers, which use it to turn off C style preprocessing. With
as, there is no need for -nocpp, because the gnu assembler itself never runs the C preprocessor.
- Disable or enable floating-point instructions. Note that by default
floating-point instructions are always allowed even with CPU targets
that don't have support for these instructions.
- Disable or enable double-precision floating-point operations. Note
that by default double-precision floating-point operations are always
allowed even with CPU targets that don't have support for these
--no-construct-floatsoption disables the construction of double width floating point constants by loading the two halves of the value into the two single width floating point registers that make up the double width register. This feature is useful if the processor support the FR bit in its status register, and this bit is known (by the programmer) to be set. This bit prevents the aliasing of the double width register by the single width registers.
--construct-floatsis selected, allowing construction of these floating point constants.
asautomatically macro expands certain division and multiplication instructions to check for overflow and division by zero. This option causes
asto generate code to take a trap exception rather than a break exception when an error is detected. The trap instructions are only supported at Instruction Set Architecture level 2 and higher.
- Generate code to take a break exception rather than a trap exception when an
error is detected. This is the default.
- Control generation of
.pdrsections. Off by default on IRIX, on elsewhere.
- When generating code using the Unix calling conventions (selected by -KPIC or -mcall_shared), gas will normally generate code which can go into a shared library. The -mno-shared option tells gas to generate code which uses the calling convention, but can not go into a shared library. The resulting code is slightly more efficient. This option only affects the handling of the .cpload and .cpsetup pseudo-ops.