Motorola PrPMC1100 CPU card

Overview

RedBoot supports the builtin high-speed and console UARTs . The console UART is the default and feeds the front panel COM1 connector. The high-speed UART signals are only available from the PN4 IO connector. Therefore, usability of this port depends on the carrier board used. The default serial port settings are 115200,8,N,1. RedBoot also supports flash management for the 16MB boot flash on the mainboard.

The following RedBoot configurations are supported:

Configuration	Mode	Description	File
ROM	[ROM]	RedBoot running from flash sector.	redboot_ROM.ecm
RAM	[RAM]	RedBoot running from RAM with RedBoot in the flash boot sector.	redboot_RAM.ecm

Initial Installation Method

The PrPMC1100 flash is socketed, so initial installation may be done using an appropriate device programmer. JTAG based flash programming may also be used. In either case, the ROM mode RedBoot is programmed into the boot flash at address 0x00000000.

After booting the initial installation of RedBoot, this warning may be printed:

flash configuration checksum error or invalid key

This is normal, and indicates that the flash should be configured for use by RedBoot. Even if this message is not seen, it is recommended that the fconfig be run to initialize the flash configuration area. See the Section called Persistent State Flash-based Configuration and Control in Chapter 2 for more details.

Rebuilding RedBoot

These shell variables provide the platform-specific information needed for building RedBoot according to the procedure described in Chapter 3:

export TARGET=prpmc1100
export ARCH_DIR=arm
export PLATFORM_DIR=xscale/prpmc1100

The names of configuration files are listed above with the description of the associated modes.

Interrupts

RedBoot uses an interrupt vector table which is located at address 0x8004. Entries in this table are pointers to functions with this protoype::

int irq_handler( unsigned vector, unsigned data )

On the PrPMC1100 board, the vector argument is one of many interrupts defined in hal/arm/xscale/ixp425/current/include/hal_var_ints.h::

#define CYGNUM_HAL_INTERRUPT_NPEA         0
#define CYGNUM_HAL_INTERRUPT_NPEB         1
#define CYGNUM_HAL_INTERRUPT_NPEC         2
#define CYGNUM_HAL_INTERRUPT_QM1          3
#define CYGNUM_HAL_INTERRUPT_QM2          4
#define CYGNUM_HAL_INTERRUPT_TIMER0       5
#define CYGNUM_HAL_INTERRUPT_GPIO0        6
#define CYGNUM_HAL_INTERRUPT_GPIO1        7
#define CYGNUM_HAL_INTERRUPT_PCI_INT      8
#define CYGNUM_HAL_INTERRUPT_PCI_DMA1     9
#define CYGNUM_HAL_INTERRUPT_PCI_DMA2     10
#define CYGNUM_HAL_INTERRUPT_TIMER1       11
#define CYGNUM_HAL_INTERRUPT_USB          12
#define CYGNUM_HAL_INTERRUPT_UART2        13
#define CYGNUM_HAL_INTERRUPT_TIMESTAMP    14
#define CYGNUM_HAL_INTERRUPT_UART1        15
#define CYGNUM_HAL_INTERRUPT_WDOG         16
#define CYGNUM_HAL_INTERRUPT_AHB_PMU      17
#define CYGNUM_HAL_INTERRUPT_XSCALE_PMU   18
#define CYGNUM_HAL_INTERRUPT_GPIO2        19
#define CYGNUM_HAL_INTERRUPT_GPIO3        20
#define CYGNUM_HAL_INTERRUPT_GPIO4        21
#define CYGNUM_HAL_INTERRUPT_GPIO5        22
#define CYGNUM_HAL_INTERRUPT_GPIO6        23
#define CYGNUM_HAL_INTERRUPT_GPIO7        24
#define CYGNUM_HAL_INTERRUPT_GPIO8        25
#define CYGNUM_HAL_INTERRUPT_GPIO9        26
#define CYGNUM_HAL_INTERRUPT_GPIO10       27
#define CYGNUM_HAL_INTERRUPT_GPIO11       28           
#define CYGNUM_HAL_INTERRUPT_GPIO12       29
#define CYGNUM_HAL_INTERRUPT_SW_INT1      30
#define CYGNUM_HAL_INTERRUPT_SW_INT2      31

The data passed to the ISR is pulled from a data table (hal_interrupt_data) which immediately follows the interrupt vector table. With 32 interrupts, the data table starts at address 0x8084.

An application may create a normal C function with the above prototype to be an ISR. Just poke its address into the table at the correct index and enable the interrupt at its source. The return value of the ISR is ignored by RedBoot.

Memory Maps

The RAM based page table is located at RAM start + 0x4000.

NOTE: The virtual memory maps in this section use a C, B, and X column to indicate the caching policy for the region..

X C B  Description
- - -  ---------------------------------------------
0 0 0  Uncached/Unbuffered
0 0 1  Uncached/Buffered
0 1 0  Cached/Buffered    Write Through, Read Allocate
0 1 1  Cached/Buffered    Write Back, Read Allocate
1 0 0  Invalid -- not used
1 0 1  Uncached/Buffered  No write buffer coalescing
1 1 0  Mini DCache - Policy set by Aux Ctl Register
1 1 1  Cached/Buffered    Write Back, Read/Write Allocate

Virtual Address   Physical Address  XCB  Size (MB)  Description
---------------   ----------------  ---  ---------  -----------
   0x00000000       0x00000000      010     256     SDRAM (cached)
   0x10000000       0x10000000      010     256     SDRAM (alias)
   0x20000000       0x00000000      000     256     SDRAM (uncached)
   0x48000000       0x48000000      000      64     PCI Data
   0x50000000       0x50000000      010      16     Flash (CS0)
   0x51000000       0x51000000      000     112     CS1 - CS7
   0x60000000       0x60000000      000      64     Queue Manager
   0xC0000000       0xC0000000      000       1     PCI Controller
   0xC4000000       0xC4000000      000       1     Exp. Bus Config
   0xC8000000       0xC8000000      000       1     Misc CPU IO
   0xCC000000       0xCC000000      000       1     SDRAM Config

Platform Resource Usage

The CPU programmable OStimer0 is used for timeout support for networking and XModem file transfers.